Computer Science 152 - Spring 1995 - Kong - Midterm 2

# Computer Science 152 - Spring 1995 - Kong - Midterm 2 -...

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CS152 COMPUTER ARCHITECTURE AND ENGINEERING EXAMINATION #2 NAME:____________________________ DISCUSSION SECTION TIME:_____________ PROBLEM NUMBER SCORE # 1 # 2 # 3 # 4 TOTAL SCORE NOTE: Please show your work CLEARLY for all problems. I hope you enjoy the test!

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PROBLEM 1: PIPELINING/HAZARDS For all five parts of this question, assume that we are using the five-stage pipelined MIPS machine described in the CS152 textbook. a . (6 points) The following is some code from Mr. Oza’s Nut Factory. Assume that the pipelined datapath has NO FORWARDING. Find the register hazards in the following code. Enter your answers in the table on the next page. Also, for each hazard that you find, classify the hazard (under “Hazard Type” in the table below) into one of the following three types: (1). The write register of the instruction in the EXECUTION stage is the same as the read register of the instruction in the INSTRUCTION DECODE stage. (2). The write register of the instruction in the MEMORY stage is the same as the read register of the instruction in the INSTRUCTION DECODE stage. (3). The write register of the instruction in the WRITE-BACK stage is the same as the read register of the instruction in the INSTRUCTION DECODE stage When designating the two instructions between which there is a hazard (under Instruction#1 and Instruction #2 below), use the number to the left of the instruction. When designating the type of hazard, use the number corresponding to one of the three hazards listed above. 1. add \$3,\$1,\$2 2. lw \$1,0(\$4) 3. and \$5,\$3,\$4 4. and \$6,\$1,\$2 5. or \$1,\$3,\$6 6. sw \$1,4(\$4) 7. lw \$2,4(\$4) 8. sub \$3,\$5,\$6
Instruction #1 Instruction #2 Register(s) Hazard Type 1 3 \$3 2 2 4 \$1 2 4 5 \$6 1 5 6 \$1 1 b. (5 points) Ben “The Hazard Buster” Bitdiddle (remember him?) says that instruction 7 might not load the value stored by instruction 6. Is this true? Why or why not? Solution: This is NOT true. The reason is that memory reads AND writes take place in only one stage of the pipeline (the MEM stage). Since the MEM stage of an earlier instruction ALWAYS comes before the MEM stage of a later instruction, memory reads/writes of earlier instructions are always completed before those of subsequent instructions. c. (6 points) Rewrite the code above WITHOUT CHANGING ITS EFFECT so that it has the fewest number of nop instructions. Again, assume there is NO FORWARDING. Solution: 1. add \$3,\$1,\$2 2. lw \$1,0(\$4) nop nop 3. and \$5,\$3,\$4 4. and \$6,\$1,\$2 nop nop nop 5. or \$1,\$3,\$6 8. sub \$3,\$5,\$6 /* Note that instruction 8 has been moved up nop nop 6. sw \$1,4(\$4) 7. lw \$2,4(\$4)

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d. (4 points) Pipeline the following circuit for maximum throughput by adding pipeline registers (by drawing vertical lines on one or more wires) at appropriate places. Use as few pipeline registers as possible. On each component, the number in parentheses is that component’s latency. THERE ARE NO WIRE DELAYS OR OTHER DELAYS IN THE CIRCUIT. None of the components are clocked; therefore, you have to make sure that, for each component, both inputs arrive at the same time.
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