Unformatted text preview: University of California, Berkeley College of Engineering Computer Science Division  EECS Spring 1998 J. Wawrzynek CS152 Computer Architecture and Engineering Midterm I Your Name: ID Number: This is a closedbook, closednote exam. No calculators. You have 3 hours. Each question is marked with its number of points one point per expected minute of time. Show your work. Write neatly and be well organized. Good luck! problem maximum score 1 20pts 2 20pts 3 15pts 4 15pts 5 30pts total 100pts CS152 S98 Midterm I 1.
20 points ID: 2 Short answers. Please provide short answers to the following questions. Correct answers are worth two point each. a b c d e f
1 points 1 points 1 points 1 points True or False. Die cost is proportional to die area2: True or False. CPU chip cost is the dominant cost in workstation system hardware cost: What instruction is used for subtract immediate on the MIPS? How would you execute a NOP operation on a MIPS processor? 1 points The MIPS uses register 31 for a link register" in function calls. What instruction is used for return"? In 20 words or less, explain why the JAVA virtual machine is a stack based architecture.
2 points g h A carrylookahead adder can complete an Nbit add in time proportional to logN and requires a number of gates proportional to choose one: logN, N, N2.
2 points and c: 1 points Given the following MIPSlike program, with memory locations a,b,
lw lw add sw r1,a r2,b r3,r1,r2 r3,c Write the same program for a stack machine: i 1 points Write a short program for a memory memory machine for the same operation: CS152 S98 Midterm I j k l m n
1 points 2 points 1 points 2 points ID: 3 What is the IEEE FP representation for 0? What is the IEEE FP representation for 1 0 2,127?
: Which operation is more complex in IEEE FP, addition or multiplication? Write the MIPS instruction representation in 1's and 0's for ADD $1,$2,$3". Hint: For ADD, func=100000 Write a formula for MIPS millions of instructions per section in terms of average CPI.
1 points o 2 points List two methods that di erent ISAs use for evaluating branch conditions. CS152 S98 Midterm I 2.
20 points ID: 4 Consider the design of a 12bit processor with the following ISA: a 12bit instructions and 12bit datawords. b Word addressing memory address refer to words not bytes. c A single instruction format, with two register speci ers, and no immediates: OPCODE 4 bits RA 4 bits RB 4 bits d 16 general purpose registers. e The following set of instructions: Instruction Arithmetic Add Arithmetic Sub Logical OR Load word Store word Branch if Equal Zero Name ADD RA,RB SUB RA,RB OR RA,RB LDW RA,RB STW RA,RB BEQ RA,RB RTL description Reg le RA Reg le RA + Reg le RB Reg le RA Reg le RA  Reg le RB Reg le RA Reg le RA OR Reg le RB Reg le RA DataMemory RB DataMemory RB Reg le RA IF Reg le RA == 0 THEN PC Reg le RB Your task is to design a single cycle processor. a Specify the type of components that you will need to build the datapath. Draw a symbol for each type and clearly label the inputs and outputs of each. Give each a name to signify its function. CS152 S98 Midterm I ID: 5 b Connect the components into a datapath and draw all connections. Clearly label all the control signals and list them again below your datapath. Don't forget the program counter. Do not design the controller. Control signals: CS152 S98 Midterm I 3.
15 points ID: 6 Consider a singlecycle processor with a set of instructions shown in the table below. Along with each instruction is its associated execution frequencies for some program X. Also shown is the delay of the critical path through the processor for each instruction. Assume that program X executes for exactly 10,000 instructions. Also assume that the processor has a clock period of 100ns. Instruction Frequency Delay load 20 100ns store 10 80ns alu rtype 60 45ns branch 10 45ns a What is the CPU time for this processor on program X? b Suppose now we are allowed to shorten the cycle time to 50ns and allow some instructions to take multiple cycles. Of course, this change would require some modi cations to the datapath and control, but don't worry about that. What is the CPU time for this new processor on program X? CS152 S98 Midterm I 4. below:
A B ID: 7 15 points Suppose that a NAND gate has the slope intercept delay model shown
Y Input Capacitance on A and B = 100fF Internal delay (intercept) = 1ns (for all transistions) Output "slope" = 0.01 ns/fF (for all transistions)
x y a In the circuit shown below, what is the delay from input 1 to , assuming that all inputs are stable at time = 0? In this part and the other parts below, ignore delay due to wires.
t x2 x1 x0 x3 x4 x5 x6 y b Suppose we construct a new gate, XOR, as follows:
A B Y Fill in the table to de ne its slope intercept delay model: Model Parameter Value A input capacitance B input capacitance Internal Delay Output Slope
c In the circuit shown below using our new gate, what is the delay from input to , assuming that all inputs are stable at time = 0?
y t
x2 x1 x0 x3 x4 x5 x6 x1 y CS152 S98 Midterm I 5.
30 points ID: 8 Recall that in class we looked at two designs for unsigned Nbit multiplication. The rst design works without a clock signal and uses N2 fulladder cells, organized as N Nbit adders. This is called an array multiplier or a combinatorial multiplier. The second multiplier design uses N fulladder cells, organized as an Nbit adder, and takes N clock cycles. This design, called a shift and add multiplier, reuses the Nbit adder N times to arrive at the result. Temporary results and operands are stored in registers some with the ability to shift. Consider the design of a third type of multiplier. This one uses only one fulladder cell, organized as a 1bit adder and takes N2 clock cycles to multiply 2 Nbit unsigned integers. a Draw a block diagram for such a design using the following building blocks: shift registers , 1 fulladder cell, 1 or more ip ops, and any simple logic gates you may need. The shift registers can be of any size needed, can shift in either direction, have all internal bits available as outputs, and can accept a new bit to be shifted in. You may assume that shift registers are automatically initialized with any value you want, but state these assumptions in part b. There are many ways to design this multiplier, but more credit will be given to simplier designs and those that try to minimize the amount of state needed. Draw the multiplier on the back of another page rst and the transfer your nal drawing to the answer space. Draw neatly! CS152 S98 Midterm I ID: 9 b Write the sequence of steps the controller must generate as we did for the shift and add multiplier in class: ...
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 Spring '04
 Kubiatowicz
 Computer Science, Computer Architecture, Central processing unit, Reg le RA, S98 Midterm, RB Reg le, IEEE FP

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