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Unformatted text preview: University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science Spring 2000 Prof. Bob Brodersen Midterm 1 March 15, 2000 CS152: Computer Architecture This midterm consists of four problems, each of which has multiple parts, so budget your time accordingly. The exam is closedbook, but calculators and one sheet of notes are allowed. Good luck! Name SOLUTIONS SID Discussion 1 2 3 4 Total Name __________________________________________________ Page 1 of 8 Problem 1: Critical Path and Delay (25 points) Throughout this problem, use the simple linear delay model presented in class. For the circuit below, assume the following delay parameters: NAND: t plh = 0.5ns, t phl = 0.5ns, t plhf = 0.002ns/fF, t phlf = 0.002ns/fF Input capacitance: 100fF Inverter: t plh = 0.2ns, t phl = 0.2ns, t plhf = 0.001ns/fF, t phlf = 0.001ns/fF Input capacitance: 50fF Wiring Capacitance: (Equal for all nodes) 5fF Y F Z X a) What is the worst case delay? Assume there is no delay at the inputs X, Y and Z. The equation for the worst case delay is as follows: .2ns+105fF*.001ns/fF (INVERTER) .5ns+205fF*.002ns/fF (NAND1) .5ns+205fF*.002ns/fF (NAND2) .5ns+105fF*.002ns/fF (NAND3 + .5ns+5fF*.002ns/fF (NAND4) = 3.345 ns Note: There is no delay at the input nodes, and remember to include fanout and wiring delay! b) Now assume that you want to generate a symbol for the circuit in part (a). Determine the following parameters for your symbol: t plh , t phl , and the load dependant delay (in ns/fF). X Y F Z First the propagation delays: t plh = t phl , = 3.345 ns. This is the same as the critical path from the last part. For the load dependent delay, since we only have a single NAND driving the output, it is the same as the NAND itself: 0.002 ns/fF. Name __________________________________________________ Page 2 of 8 Now consider the following circuit and the following parameters: Register: t clktoQ = 0.6ns, t setup = 0.5ns, t hold = 0.2ns NAND: t plh = 0.5ns, t phl = 0.5ns c) What is the maximum frequency at which this circuit will operate correctly? Ignore any load dependent delay. The critical path is from either register through all three NANDs, which corresponds to the clocktoQ of the first registers plus the propagation delay of the three NANDs plus the setup time of the last register. Therefore, F max = 1/(0.6ns+1.5ns+0.5ns) = 385 MHz d) If the clock signals are skewed so that φ 1 arrives 0.2ns before φ 2 which arrives 0.2ns before φ 3 (such that φ 1 φ 2 = φ 2 φ 3 = 0.2ns), what is the maximum frequency at which this circuit will operate correctly?...
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 Spring '04
 Kubiatowicz
 Computer Science, Computer Architecture, Cycle Time, Central processing unit, Delay, Register file

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