Computer Science 150 - Fall 1997 - Fearing - Final Exam

Computer Science 150 - Fall 1997 - Fearing - Final Exam -...

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1 of 9 Problem 1 FSM Design Problem (15 points) 1. In this problem, you will design an FSM which takes a synchronized serial input IN (presented LSB first) and outputs a serial bit stream OUT which represents the input plus 3. For example, if the input were the output stream would be . (Note that there is an output bit for every input bit. In the idle state on RESET, a zero is output.) Hint: the state machine needs to keep track of the carry bit. [8 pts.] a) Complete the state diagram for a Moore type FSM. Be sure to specify labels on transitions, and out- puts. [7 pts.] b) Complete the state table for the Moore FSM which implements the plus 3 function. 1010 2 1101 2 IDLE S 1 S 6 S 5 S 4 S 3 S 2 S 0 OUT=0 RESET IN IN Input IN Present State Next State Output OUT 0 1 S0 0 1 S1 0 1 S2 0 1 S3 0 1 S4 0 1 S5 0 1 S6 2 of 9 Problem 2 FSM Design Problem (10 points) Design a Moore FSM which outputs a single high pulse of width one clock cycle every time the synchronized input signal START changes from 0 to 1. [7 pts.] a) Show state diagram: [3 pts.] b) Show schematic for this FSM using type D FF(s) and minimal extra gates.
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3 of 9 Problem 3 FSM/Microprogram Analysis (20 points) [12 pts.] a) Complete the timing diagram for the computer data path and control unit shown on the next page. All components are synchronous. The microprogram ROM contents in Hexadecimal are: [2 pts.] b) Label the timing diagram with the micro program address. [6 pts.] c) List, in register transfer notation, the data transfer occurring at and after the noted clock edge.
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This note was uploaded on 05/17/2009 for the course CS 150 taught by Professor Staff during the Spring '08 term at Berkeley.

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Computer Science 150 - Fall 1997 - Fearing - Final Exam -...

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