Computer Science 150 - Fall 2001 - Subramanian - Midterm 1

# Computer Science 150 - Fall 2001 - Subramanian - Midterm 1...

This preview shows pages 1–2. Sign up to view the full content.

CS 150, Midterm #1, Fall 2001 CS 150, Fall 2001 Midterm #1 Dr. Vivek Subramanian Problem #1 You are given a negative edge triggered D flip-flop as shown on page 1-19 of the notes on sequential logic. a) Design the combinational logic necessary to convert this flip-flop into a negative edge-triggered J-K flip-flop. Leave your solution in sum-of-products form. Write out the equation for the combinational logic block, and draw the block connected to the FF below. Equation: b) Assume the setup and hold times for the D-FF above are 20ns and 10ns respectively. What is the minimum propagation delay for the D-FF for it to meet correct timing criteria? Why? c) Suppose the propagation delay for the D-FF is 20ns and the clock frequency is 10 MHZ. What is the maximum delay per gate allowed in the sum-of-products combinational logic block that you designed? Give a reason for your answer, and show your calculations. Assume that all gates in your combination block have identical delay. Also assume that J' and K' are available for free (i.e., no delay in inverting the J and K signals). d) Recalculate the SOP equation describing the combinational logic block assuming that you must now also implement a

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 05/17/2009 for the course CS 150 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

### Page1 / 4

Computer Science 150 - Fall 2001 - Subramanian - Midterm 1...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online