Electrical Engineering 40 - Fall 1998 - Howe - Final Exam

Electrical Engineering 40 - Fall 1998 - Howe - Final Exam -...

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1 University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EECS 40 Final Examination Fall 1998 Prof. Roger T. Howe December 14, 1998 Name: ______________________ Student ID _____________ Last, first Guidelines 1. Closed book and notes; 3, 8.5” x 11” page (both sides) of your own notes are allowed. 2. You may use a calculator. 3. Do not unstaple the exam. 4. Show all your work and reasoning on the exam in order to receive full or partial credit. Score Problem Points Possible Score 1 25 2 20 3 20 4 20 5 15 Total 100
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2 1. Digital Logic Gate [24 points] A’ A x , [ μ m] y , [ μ m] 6 0 8 4 2 10 12 B B’ 0 2 4 6 8 3 2 1 5 4 Process Sequence : Starting material: phosphorus-doped silicon, concentration 5 x 10 17 cm -3 1. Deposit 500 nm of silicon dioxide and pattern using the oxide mask (dark field) 2. Grow 5 nm of thermal silicon dioxide. 3. Deposit 500 nm of boron-doped polysilicon and pattern using the poly mask (clear field). 4. Implant boron and anneal (depth 250 nm and concentration = 1.25 x 10 18 cm -3 .) 5. Deposit 500 nm of silicon dioxide and etch 505 nm of oxide using the contact mask (dark field). 6. Deposit 500 nm of aluminum and pattern using the metal mask (clear field). Given : polysilicon sheet resistance: R = 25 / , ε ox = 3.45 x 10 -13 F/cm, R on = 150 (on resistance for MOSFET)
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9 μ m 1 μ m Oxide Mask (dark field) Poly Mask (clear field) Metal Mask (clear field) Contact Mask (dark field) 17 μ m 1 μ m 3 μ m 15 μ m 3 μ m (a) [6 pts.] Sketch the cross section 9 11 12
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Electrical Engineering 40 - Fall 1998 - Howe - Final Exam -...

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