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Unformatted text preview: UNIVERSITY OF CALIFORNIA College of Engineering
Department of Electrical Engineering
and Compute: Sciences Professor Oldham Fall 1999 EECS 40 — FINAL EXAM
13 December 1999 Student ID:
TA: C! Kusuma
El Chang Guidelines:
(a) One page of notes allowed (both sides).
(b) You may use a calculator.
(c) Do not unstaple the exam.
(d) Show at! your work and reasoning an the exam in order to receive full or partial credit. (e) This exam contains 16 pages plus the cover page and 2 sheets of scratch paper included at the end of
the exam. You can remove these from the rest of the exam if you wish. 111 0d 11 (3) Write 2 nodal equations sufﬁcient to ﬁnd voltages A and B. (b) The switch closes at t = 0 (after a very long time open). Write 2 nodal differential equations describing
VI and Vy . ILL 3 L2 BC’ﬁDrg gwgqidﬂ 0/0534) m Voiﬁg’ge dam5 C; om! C?“
WK. MUM UNA/940— M (IS COQYLEZ'ILLCLQJ (43 {*[email protected]/ 5’10 Cull/WW f/DWJ' C, amf C; 10116 (c) Vx(r=o+) = O V
,.‘l VyU: 0+) = L V
V,
Vx(t—)oo) = 1' Vy(t —9 on) = 2of16 0 le Nerd t In a postBig Game Nerd Competition, teams from Stanford and UCB were asked to draw logic diagrams to
implement the following function: T=A+BC The Stanford team came up with the following design based on NOR gates
,r':;“"""' Design SS . The Berkeley team came up with the following design based on NAND gates: C D
B
A TBB
E
Design BB (3) Fill out the truth tables opposite to evaluate T53 and T33. (b) Do both circuits function as desired? (c) Define the unit gate delay of the NOR gates as TNOR and unit gate delay of the NAND as TNAND. Assume the outputs, T, are loaded by similar gates. What is the delay of the Stanford circuit and what is
the delay of the Berkeley circuit (in terms of TNOR , TNAND )? rt ...‘~— 30116 WM (3) FILL OUT WITH ZEROS AND ONES
(b) Function correct?
(yes or no?) (c) Delay 40116 SS Circuit BB Circuit " “"' (a) (b) (c) (d) e Nerd n e t — ils ' (Independent of Problem 2) The schematic of a CMOS inverter analyzed in Lecture 25 is shown in the ﬁgure below. Note the unit
gate delay is 16.5 ps when the inverter drives an identical inverter. Using the same CMOS technology, you are to design (that
means draw the schematic ot) a 2—input NAND gate [NOT
a layout please!]. Please size the devices for equal worst case rise and fall times, and use 1.50.18 as the pchannel
device size. VDD = 1'8 RN = RP = 3.1K 0.69RC = 16.5ps
1.5/0.13tum/um) 0.?5
m (Hm/Pm) Find the input capacitance and the output resistance of such a NAND gate (worst case). Compute the
gate delay assuming the NAND gate drives the inputs to identical NAND gates. Ignore drain—bulk and
interconnect capacitance. Now draw the schematic of the NOR gate and indicate device sizes needed to get equal (worst—case) rise
and fall times. Again use 1.52’0.18 as the pchannel device size. Find the input capacitance and the output resistance of such a NOR gate. Compute the unit gate delay
assuming the NOR gate drives the inputs to identical NOR gates. Ignore drain—bulk and interconnect
capacitance. For dim. TWEr'tQJ‘ Tm W ﬁgure. gloom, 16.593 =
C : Willa“: 0.64 RC. ———><’L= C Cap+Cau> == £6,5P5 / CO.6‘1*E§.\L<§£D
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NMOSE=_L5_
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schematic of NAND gate
(b) COP: 5‘14 fF CGN= 5‘4 {F
R = :3, l K Unit Gate Delay = LS schematic of NOR gate 5\ ﬂ: CGNz ix ﬂ: R: 5‘1 K UnitGateDelay= 275' 138 (d) cc}, = 60116 1V em 3 \{f
X _
(a) c V — ..._
2v 9 2m 0 9 5V Power delivered by lmA source = “l m W
_ .._.... I c Power dehvered by 2111A source = 0’]
_ ImA 2m
IOpF Y V = 3V
(b) V .
2V 9 C2. 3K J3 OCOPF Power delivered by imA source = Fl m W;
1  ._H
Energy stored in C2 = 5 P J
"K v .
10K '5 .___ ’ .
(c) rm]— Capacitors are initially uncharged. V V — l 9 Z V/
. . . = is
1:31: FInd VX long after the swrtch rs X
6V . "  1‘
2p}: ZPF closed. Fmd peak power PMAX PMAX = g)" in, w
delivered by the voltage source.
{(1) Assume the 4 diodes are perfect V _ g _/
rectiﬁers. (a) What is VX when a) X _ 
= 0 ' ‘
VI 5V . (b) What 15 VX when b) VX : RISK/f
v1 = +5V?
(e) VX = H 70116 W if X
\l 5V
2V —' #7
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 we? when CQPSKLJDTS ach er shor+ circuﬂng) so . :ﬁJBQ a: w
PmX R. mJK— 3,..bm VyZ’SV «Dar Parjr Us) 5931:4512! C60 _ 3/5, I ' Olré HR ‘5qu “ma: V; : LN Vx: 3v+\v+2v+4\/=<§\/ ‘
80115 (3w Shouldn’ a" have c/cwe ﬂodfﬁ/ ﬂﬂdéﬁﬁs) Inverter A is a CMOS inverter with effective output resistance of 1.5K. VDD = 2.5V and VT: = 0.7,
VT}, = 1.8V. The input capacitance is 5 fF, ‘VIN was zero for r < 0 , then a pulse generator (with very low output resie tance) produces the input waveform shown above. (a) Sketch the general form of VOUTU) . (b) Calculate VOUT at t = 0+,t = 1 nsec,and r = 2 nsec. (c) Resketch VOUT(+) very carefully and neatly. 901‘16 503 v 'Ho‘ w! &
em 11 w t _ ___
(a)
t(nsec)
0’) b.1) Vow“ = 0+) = :2 o 5 V VOUTU = 1 uses) = o V
b3) VOUTU = 2 nsec) = L at 61 V
(0 VOUT t (nsec) 100f 16 I v in 'v Find the The’venin equivalent circuit for each of the following (a) (b) (c) . (d) I 1K I “K at;
A 2K I Souwca pug—“WU
I  Wnsformmﬁ'om Ltv
1.
B ' 17. Pal/ii;
' 1K 2m 
I. _ _ _ _ _ __ _. .J
623 #633“
r — — — — — — — . are. L:
I W ClmA 2K p I
A I C— D c_ .b
SI‘mP [I' Caffcptt‘t I
I 6K 3K 1 ﬂ 6" c; 3v 3"
B l o '——'
 1K 2V  (at; b
L h u u _ _ ..... _ .1
it av
E ohm/1M} 'H
I" _ _ _ _ _ _ _ _ '— "I I I '
A I I I I A“ ' B I (Opamps are ideal)
VIOLA.) ftgr— Uot'ff‘(ﬁc _I = [Km 11of16 eméW n W VThev ' (a) w: 2:
E
H (b)
VTH = 4x 3 1
Rm = W ’
(c)
VTH = 195— VI
RTH = I K
(d)
VTH = QK/ 12 of 15 em and 'v We are designing a CMOS logic circuit with the latest devices C 2 m: that use L = 0.15pm. An GP inverter schematic is shown for W = IN CGn = “F the basic inverter OUT RP = 3.5K
R = 3.5K We need to drive an interconnect wire going across the chip with a capacitance of 192 fF. (a) Estimate the stage delay (time to switch the output from zero to VD D/ 2 with the input going from VDD to 0) if this inverter drives the wire directly. The 192fl= load is connected to the node labeled
‘60UT1!. (b) Suppose we insert two “buffer inverters” that have larger W/ L (and therefore, lower RP, Rn) to drive the load capacitance faster: 2
For Inverter A: .ZY‘N = (m R LI‘
E = —4
I Ci=192fF Llp 0'15
=— For InverterB: %N = W _ i
flp ' 0.15 Now we suffer 3 stage delays! But let’s compute them — maybe it’s not so bad. Assume the load on
I0 is the gate capacitance of IA and similarly that the load on IA is the input capacitance of EB. (b.1) Compute CG” and CGP for IA and I8.
(b2) Compute RP and R,1 for IA and IE. (ce) Find the unit gate delay for all 3 stages (input step VDD —> 0 or 0 — VDD and output moving from 0 to
VDD/Z or VDD to Von/2). (f) Compare total gate delay with that of part (a). 1301'15 lm7W he 0. GqRC": .GW35K x m Md“ w 1 a»
I Cwm = 192 fF Unit gate delay = 5&9 El ps
('3)
C T Kl (0 6L"!
.  CGn
R.'{’ 0L Ll CGp
RP
R . (LC: gec‘ygtg‘lcx In“:
(c) —_ .69 I delay Unit gate delay = AP;
(d) I b g» IQ,“ch :,eqx879xw~¢F
Unit gate delay = M
delay 0:) —_ {mint ,6qu X191“: (0 Total of(c)+(d)+(e) (:37 F §~ versus (a) Lfétf 95; 1401’ 16 P blem 8 Te lo in
The layout of a CMOS logic circuit is shown below. Also shown on the page opposite is the crosssection E
E of the chip. 8 Metal i NWe I Polysiiicon Comm 3 (clear ﬁeld)
1 (dark ﬁgld) (dark ﬁeld) (01637 ﬁeld) (dark ﬁeld) @Qmmgﬂ u A u . ’ t u a o . t t. The CMOS process is: (1) Start: pType Si wafer (2) Well mask, implant donors (3) Grow field oxide 05th (4) Pattern oxide (oxide cut for thin oxide)
(5) Grow gate oxide (6) Deposit 0.5mm polysilicon (7) Pattern polysilicon (8) Two select masks with implants (masks not shown)
(9) Deposit 0.5ttm oxide (10) Contact mask, etch oxide (1]) Deposit 05th metal (12) Pattern metal (a) In the space provided, draw crosssection AA. Use EE as a guide fOr scale.
([1) Draw crosssection BB. (c) Label the inputs and outputs of this circuit on the ﬁgure above. (Note that there are 6 wires entering
from the left and of these, only 2 are labeled, namely VDD and ground. You are to label the others and use these labels in part d.) ((1) Write the logic function of the circuit (for example, OUT = (A + B) » E). 15 ONE Crosssection AA 0)) ‘ (c) (Label ﬁgqu on opposite page.) ~ _ V‘D (d) ' Logic Equation OUT = A “ B ' c 160:16' ...
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 Spring '07
 ChangHasnain
 Electrical Engineering, Logic gate, unit gate delay

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