Electrical Engineering 141 - Fall 1995 - Rabaey - Final

Electrical Engineering 141 - Fall 1995 - Rabaey - Final -...

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EECS 141: FINAL FALL 1995 1 University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 203 McLaughlin MWF 10:11am e141@zabriskie EECS 141: FINAL FALL 1995 For all problems, you can assume the following transistor parameters: NMOS: V Tn = 0.75V, k ’ n = 20 μ A/V 2 , λ = 0, γ = 0.5 V 1/2 , 2 Φ F = -0.6V PMOS: V Tp = -0.75V, k ’ p = 7 μ A/V 2 , λ = 0, γ = 0.5 V 1/2 , 2 Φ F = -0.6V Bipolar NPN : β F = 100, V BE(on) = 0.7V, V BE(sat) = 0.8V, V CE(sat) = 0.1V Wiring: Aluminum: C parallel-plate = 0.03 fF/ μ m 2 ; C fringe = 0.045 fF/ μ m, R sheet = 0.05 /o, L alum = 0.4 pH/ μ m Polysilicon: C parallel-plate = 0.06 fF/ μ m 2 ; C fringe = 0.045 fF/ μ m, R sheet = 10 /o For all problems, you maty assume that the transistor lengths indicated are the effective lengths (L eff ) or, equivalently, that LD = 0. All questions are worth 15 points. NAME Last First GRAD/UNDERGRAD 1 2 3 4 5 6 7 Total
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EECS 141: FINAL FALL 1995 2 PROBLEM 1: Logic / Arithmetic Shown in FIG. 1 are two building blocks for an adder. a. Derive the logic function of each of the outputs U , V , X , and Y . b. What logic style is used for the implementation of this function? Where does it differ from the standard implementation? c. Would a single PMOS transistor suffice? Why or why not ? FIG. 1 Buidling blocks U V X Y a i b i b i+1 a i+1 a i+1 b i+1 a i+1 b i+1 a i b i a i b i a i+1 b i+1 a i+1 b i+1 U: V: X: Y:
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EECS 141: FINAL FALL 1995 3 d. Draw a block diagram on how you would connect these modules to create a 16-bit adder. e. Derive an approximative expression for the worst-case delay of your adder (for N bits). f. Describe one approach on how these blocks could be used in a better-than-linear adder.
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EECS 141: FINAL FALL 1995 4 PROBLEM 2: Power Consumption A capacitor of 20 pF is being charged through a switch with a constant on-resistance of 10 k (FIG. 2a). a) A voltage step of 3 V is applied at the input, as shown in FIG. 2b. Compute the energy that is stored on the capacitor when the transaction is completed. b) Compute the energy dissipated in the switch during the transaction.
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Electrical Engineering 141 - Fall 1995 - Rabaey - Final -...

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