EECS 141: Digital Integrated Circuits, Fall '96
1
University of California at Berkeley
Department of Electrical Engineering and Computer Science
EECS 141: Final Exam, Fall '96
Renu Mehra
19th Dec. 1996
Please PRINT your name on each sheet. Write clearly.
Use the space provided to answer all questions. Use the back side if needed.
Name:
(last)
(first)
Signature:
SID:
T
ransistor parameters:
Neglect body effect and
channellength modulation.
NMOS
PMOS
V
T0
0.7
1.0
k'
n
, k'
p
60
μ
A/V
2
30
μ
A/V
2
L
d
0
μ
m
0
μ
m
Grades
Problem #1 (18 points)
Problem #2 (16 points)
Problem #3 (18 points)
Problem #4 (16 points)
Problem #5 (12 points)
Problem #6 (10 points)
Problem #7 (12 points)
Problem #8 (18 points)
Total (120 points)
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Name:
EECS 141: Final exam, 19th Dec. '96
2
Problem 1.
For each of the following statements, indicate where it is true or false. (18 points)
(T / F)
1(a)
The speed of a ring oscillator can continuously be improved by increasing the
W/L ratio of the inverters.
(T / F)
1(b)
Decreasing supply voltage helps to alleviate the velocitysaturation problem.
(T / F)
1(c)
The load capacitance of a static CMOS gate has no effect on its VTC.
(T / F)
1(d)
A
φ
nblock dynamic gate will not have any charge sharing problems if only
0
→
1 transitions occur at its inputs during evaluation.
(T / F)
1(e)
The transistors in a Manchester carry chain should be sized progressively larger
from the input to output to reduce the propagation delay.
(T / F)
1(f)
Lowswing buses save power and reduce propagation delay at the same time.
(T / F)
1(g)
The delay of a static inverter is minimized if (W/L)
p
/(W/L)
n
is equal to
μ
n
/
μ
p
.
(T / F)
1(h)
Silicided poly lines reduce the delay of a wire by decreasing the capacitance.
(T / F)
1(i)
The maximum propagation delay between two latches determines if a race con
dition will occur due to clock skew.
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 Electrical Engineering, Direct Current, Volt, 19th Dec

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