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Unformatted text preview: Problem 2: Device Analysis
Consider the device conﬁguration ofFIG. 2. M1 is University of California
College of Engineering
Department of Electrical Engineering
and Computer Science 3" J. M. Rabaey TuTh9:3o11am
. [email protected] EECS 141: FALL 00 —MIDTERM 1 For all problems, you can assume the following transistor parameters (unless
otherwise mentioned): NMOS: VT,1 = 0.4, k’n = 115 HANZ, VDSAT = 0.6V, x = 0,1 = 0.4 V1’2,2tI)F = 0.6V
PMOS: _ VTp = 414V, k’p = 30 “m2, VDSAT = —1v, 1 = 0, 7 = —0.4 V”, 2:1)F = 0.6V Problem 1: (5.5, Problem 2: 100
Problem 3: 725 Total 2 Cg EECS l4l: FALL 00 —MDTERM  l PROBLEM 1: Transient Response FIG. I Dlgital circuit Consider the circuit of
FIG. 1. All the transis
tors are originally mini
mumsize devices. Use
the transistor parame ters indicated on the ﬁrst
page of the. midterm. V01) = 2.5 V. CL = 30 fF. Leakage effects should not be considered in this question. a. Assume that the initial voltage on V0,” = 0. A step from 0 to VDD is applied at the input. Determine the ﬁnal voltage at Val”. \éiuT:\/Z:VI:VGSF T 12> Tzvbnfvi VT: VT“ 4— '3’ "Edi:+VSB  .l—zépj W
£341 IsaW2C? 2.5w VI 1 0,4 +0.91! ‘E0.c,+\/, » E]
(2.4!» w): (o. 4‘15.“ v.) 2.4:2‘» 4.32% +V‘T[C3.1Co>(0C9+ V!)
vf— 4.9th +s.ew=o your (ﬁnal) = I. 8.43 V 3 b. Assume the following parameters for the minimum size transistors: Req = 15 k9, Cg: =
ng = Cgb = ”F. C3!) = Cdb = 2 E. To determine the propagation delay of the circuit, we
will use the equivalent resistorcapacitor diagram. Draw the equivalent circuit including all relevant resistors and capacitors and their values. EECS 14!: l‘ALL UO —MIDTERM  c. Determine the propagation delay between input and output for a step at the input from
0 to Vdd. €53 7:": EﬂLCI ”Ref: + seq/c3
: CISkX%¢A‘5 + Gordan?) +£95©<334§ : 3.l05 ms
679 ‘6 =0G‘9T': 2.142. as (”(for Vin going from a —) Vdd)= Z, 14 '2 n S (1. Assuming that the transistor capacitors and conductance increase linearly with the
width of the transistor. Determine the size S of the transistors that reduces the propagation
delay by a factor of 2. All three transistors are to be scaled by the same factor.. @ t5:<%a( (oF S + CL) + (3%,, ég,s+cL) + <§%><3‘C'5 + CL) "C __ ’2‘" Z5 é‘[3c+'%z +49]:<‘.§) GS+BO + ‘23 4—6963—1— ‘35 + 3;]
7¢.Ss§=l%’0 5: 2.3573 @ s=(\v’lL)!(W’lL)orig= Z. 33 3 EIECS MI: FALL 00 —MIDTE[{M l Problem 2: Device Analysis Consider the device conﬁguration of FIG. 2. M1 is
a minimum size transistor (assume W/L = l). eled by the uniﬁed model.. a. Write down the equations (and only those) that
yOu need to determine the voltage at node X. Do NOT plug in any values yet. BE COMPLETE and CONSIDER ALL POSSIBLE SOLUTIONS FIG. 2 CMOS inverter with resistive load
Determine for each solution when it is valid. m No‘i'icg “hind VGS:VDS M, {5 a/mm/J Sari'aras‘i'ian :9 r V9.3 {. Said F “life/1 2 V
Assume the transistor parameters given on page I
of the midterm, but assume that v = 0 (no body l' R
effect). Assume a short—channel transistor mod X
M1 VMi‘CM CAL/£18!" {‘2’} (v5.51 if i” amazes/=0. ‘{ b. We would like to place VX at 0.8 V. Determine which of the above soltuions is valid.
Draw the (approximative) load lines for both MOS transistor and resistor on the diagram provided. ZCAGCIJ‘AJI C.
(aim altmcﬁ on V): in ‘j—‘imear Menuhinx on 165 .31 val 5x} sad. EECS 141: FALLUU—MIDTERM ] c. Determine the value of the resistance required to place X at 0.8V. I? chonaw, M; samec» since I'Vbsl‘lvbwpl 2:93. : (43(30459 )(aﬁwav a d. Assume now that the Afaetor of the PMOS is different from 0, in contrast to what was
assumed so Far. Determine qualitatively if the voltage at node X will go down, or up, or
remain unchanged. Explain your anSWer. B Up 1+ 9‘ 35C) ) +LM I I‘nCMoL‘SC 5' ) drwah
[3/ Down P 3 Wu: ,1: wrfcn‘l‘ ‘H‘l rot15L e
E} Unchanged _.__) IR citDP ell—cross E. [5' lo: 4f ——3 chm are. vx Muff dccm” EECS 111: FALL 00 —MIDTERM I 5 PROBLEM 3: Technology Scaling Consider a CMOS inverter followed by a wire on length L. Assume that in the reference
design, inverter and wire contribute equally to the total propagation delay 1‘!)ch You may assume that the transistors are velocitysaturated. The wire is sealed in line with the ideal
wire scaling model. Assume initially that the wire is a local wire.
a. Determine the new (total) propagation delay as a a function of rpmf, assuming that tech nology and supply voltage scale with a factor 2. Consider only ﬁrstorder effects. Delay 0? buﬁ‘éx SeaJCS as {/5 Dellaw a": lo cal botres SCaLleS a; l
t Ll pﬁr _ fir—51“. ”69:124.? H i
‘6? I *p—2_— —i' fpwir't '* Li + Z .— Ll fen(5F b. Perform the same analysis, assuming now that the wire scales a global wire, and the
wire length scales inversely proportional to the technology. 4 Dallas? of stained coin—c SCcLiES as S e __ tPr’C‘i' +_ tPW—‘FDIQ: 513.1:
“ Li Z q Pfizrgi c. Repeat b, but assume now that the wire is scaled along the constant resistance model.
You may ignore the effect of the fringing capacitance. 3
Denim], 01f ﬁioénl mire (Conslnnf‘ rESiS'l'qricﬂ) sealeyas S “twat! {Pvtf3. :13:
so"? "2—8 4 secs H I: FALL 00 —MIDTERM I ' 6 {Pref 9896396 (1. Repeat b, but assume that the new technology uses a better wiring material that reduces
the resistivity by half, and a dielectric with a 25% smaller permittivity. ”if—Lift” 4— tmrfaexcé K5 5 d 1'8«(ECI+FI.(_
(“C/SiS‘f‘I'VI'i‘I {P2 ’32], few! 6. Discuss the energy dissipation of a. as a function ofthe energy dissipation of the origi nal design Erf !
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E: ‘(2 EraF f. Determine for each of the statements below ifit is true, false, or undeﬁned, and explain
in one line your answer.
 When driving a small fanout, increasing the driver transistor sizes raises the short—cir
cuit power [email protected] F  U Okraiﬁ'vt‘na 1L1 eu'f'PM'f' muse: th‘ au'i'f’d 6“”
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 Reducing the supply voltage, while keeping the threshold voltage constant decreases the
shortcircuit power dissipation® F  U Less “time when £39441 +.—.,, “S'S'ibrs
m on
 Moving to Copper wires on a chip will enable us to build faster adders. T .® U
RC cut (an! :5 yin{5 an I‘llSue 14; SLor'f' wires
 Making a wire wider helps to reduce its RC delay. T  F @
0,137 LUAen ﬁriagi'n {.5 m1 riﬂ'u—a , ErrUP mahks *1 W'HQ 3"“ {vizier
 Going to dielectrics with a lower peéiiittivity will make RC wire delay more important. “J” “I?"
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RC Scales airman in him 5mm. 120941 “5 C *‘3’ tiara a": Rmm'sS
‘Hd. SumPu. EECS I4 E: FALL 00 —MlDTE[{M l 7 ...
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 Spring '08
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 Electrical Engineering

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