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Electrical Engineering 141 - Fall 2000 - Rabaey - Midterm 2

Electrical Engineering 141 - Fall 2000 - Rabaey - Midterm 2...

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Unformatted text preview: University of California College of Engineering Department of Electrical Engineering and Computer Science _," J. M. Rebaey 'IhTh9:30-llam [email protected] EECS 141: FALL 00 —- MIDTERM 2 For all problems, you can assume the following transistor parameters (unless otherwise mentioned): NMOS: an = 0.4, k’n = 115 W2, VDSAT = 0.6V, 1 = 0, 7= 0.4 V1”, 2(1)}: = -0.6V PMOS: va = -o.4v, 14'}, = -30 W2, VDSAT = -w, a. = o, 7= -0.4 v1”, 2(1)]: = 0-6V SOLUTIO MS Last First —— Problem 1: 87 Problem 2: H Problem 3: Q) EECS 141: FALLflor-MIDTERMZ 1 PROBLEM I: Inductance Vin GND FIG. 1 Large Capacitance Driver Consider the simple cir- cuit of FIG. 1, where the inverter is implemented- using complimentary CMOS. Assume that the transistors in the inverter can be modeled as con- stant linear resistors (when on). VDD = 2.5 V. CL = 25 pF. . a. Assuming a 1->0 transition at the input, determine the transistor resistances that will result in a 0 to 90% transition on the output of 5 nsec.. legion. NHOB ‘O‘Mcc “with. 6. P‘QQ‘WKP JIFQHSK is)“; Rimes 1:, RNMOS = N- A- RPMOS = ‘33? 5)- CL 1'). Draw the current drawn from the supply as a function of time during this low-to-high transition, and derive the appropriate equations that describe that behavior. Assmne that the input signal has a very steep slope, and that the transistors switch instantaneously. O EECS 141: FALL 00 — MIDTERM 2 c. The supply rails of the driver (VDD and GND) are connected to an external off-chip supply with a value of 2.5 V through bonding pads and wires with a total inductance of 7.5 nH. Draw the VDD and GND signals as a function of time for the transition described above, and annotate some meaningful values. You may assume that the intro- duced hiductances do NOT impact the results of part b. d. Faced with the emerging problem, rank-order the following remedies in order of poten- tial efi‘ectiveness. 1 being the most effective, 4 the least - Introduce a capacitance of 25 pF between VDD and GND. IE - Increase the 0-90% rise/fall times at the output with a factor of 2 by reducing the transis- tor sizes. E - Slow down the input signal to a fall time of 1 nsec. [3 re“ we): ”Q‘V'jl‘t" SP‘kfi. — Use copper instead of aluminum for the supply distribution network. LTtl EECSI41:FALLOO—MIDTERM2 3 Problem 2: Logic and Energy J ari Tukkola, a cellular phone designer at Nokia, has come up with abus-driving approach that he believes is going to both decrease energy consumption and increase performance. To deliver the high performance, he has started from a dynamic bus approach as shown in - FIG. 2 for bit 1‘. VDD is set at 2.5 V. FIG. 2 Dynamic bus architecture (bit i) a. Draw a timing diagram explaining the operation of the circuit (for the clock and input signals shown below). b. The switching threshold of the bus fanout inverters [NV has been optimized for optimal performance. Explain what Jari did to achieve this, and why. . (“/7139 n) mama” Vu 45'»:qu “manual? *3 mmug) (nu/t)... W33 Lemme: we can) can about «u. Ho summon an m land (or l-i'o transition (1+ HM. Mood) and H53 SP‘Z‘JS UP “fkafl' +r‘MS "+\lom EECS 1411 FALL 00 -— MIDTERM 2 4 c. For a bus width of N=4, determine the average energy dissipated per clock cycle for the whole bus, assuming that each input bit has a 50% chance of being a zero or a one. You may assume that the capacitive load of the bus wire C L,- = 10 pF dominates all other capac- itances (including the clock capacitance, and the driver inverter). \\ H’ 1'0" air HM. Input Consumes. We”... a. I does “of (9 5“ 4' °5 “(~th = ”SP—T J /‘r .1 N [I H Prohué o Em= W9 93 d. Jari believes that he could reduce the average energy dissipation of the bus if he would modify the circuit along the lines of FIG. 3, which replaces the driving inverter by a NEXOR. The logic block F outputs a “1” if the number of “0' bits in the input word is larger than the number of “1” bits. For instance, F= l, ifIn = 0010; F= 0, if In = 0011 or In = 11 10. Explain why this idea of Jari might not be a bad one after all. V FIG. 3 Modified DD dynamic bus architecture (bit I") @ flmlfldflmfl less "Pan's on We bufi 4 “‘3'." 0" "Mm“ Va" down! mqnmfl we. mud to WW mama”, Mr dcswcd. Thwioret transmitted 1‘9 shoutd lat. le-Hr whom... .. lat-,0; B's should be. marred Hence ‘5: invert-er it F50 Burfo’ if F5 l EECS l4l: FALL 00 — MIDTERM 2 @ e. Design the gate that implements the logic block F. Derive first the required logic func- tion, and consequently implement the gate in static complimentary CMOS. Make sure to size the transistors appropriately (this is, take into account the 3 times lower driving capa- bility of the PMOS devices compared to NMOS, and assume that the gate has to have a. driving capability equal to a minimum-sized NMOS inverter). . . _ r: a agz; + £56 +3 E35" @513 JMJ"“+7 RM e. Still assuming that each input bit has a 50% chance of being either a zero or a one, determine again the average energy dissipated per clock cycle. (WARNING - THIS MIGHT TAKE TIME TO FIGURE OUT. RESERVE THIS FOR DESSERT). Easiest“ Safari-Jew is % maize “flu. +rM-“Hx MC; Mal Com-[- 1?}. was lfleflod I Z- . 5 v ”3 32 gens Inc—Ere) 20 new EECS 141: FALL 00 — MIDTERM 2 ' 5 PROBLEM 3: Dynamic Logic Consider a conventional 4-stage Domino logic circuit as shown in Figure 6 in which all precharge and evaluate devices are clocked using a common clock d). For this entire problem, assume that the pulldown network is simply a single NMOS device (i.e., each Domino stage consists of a dynamic inverter followed by a static inverter). Assume that each gate has a propagation delay of TIZ (with T a time unit). Hence, the precharge time of the dynamic gate is TIZ, the evaluate time of the dynamic gate is T12 and the inverter low- to-high and high—to—low transitions are each TIZ. Assume that the transitions are ideal (zero riser’fall times). Domino Stage FIG. 4 Conventional Domino Dynamic Logic. Assume the pulldown network is a single NMOS device (i.e., each Domino stage consists ofa dynamic inverter followed by a staticinverter) (a) Complete the timing diagram for signals Out}, 0mg, 011:3 and 0%,. EECS 141: FALL 00 — MIDTERM 2 7 Now consider the follmving variation of the circuit where the evaluate switch of the later stages have beeu removed. Domino Gate FIG. 5 Conventional Domino Dynamic Logic with the evaluate switches removed In the later stages. (b) Assume that the clock 4: is initially in the precharge state (¢=0 with all nodes settled to the correct precharge states), and the block enters the evaluate period (¢=1). Does the removal of the evaluate switches help or hurt the evaluation. Explain. 4 l 4 ( hit/TX) H?) peep-gag 6PULL-FWWF‘V Tip/(g (c)Assume that the clock in is initially in the evaluate state (¢=l), and the block enters the precharge state (4: = 0). Does the removal of the evaluate switches help or hurt the pre- charge. Explain. - A H. l PM???) *9 HZELW zzar9ce‘s ' [a NEE—'12.: PWWM EECS 141:FALL00—M[DTERM2 3 ...
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