Electrical Engineering 141 - Spring 2002 - Rabaey - Mid 2

# Electrical Engineering 141 - Spring 2002 - Rabaey - Mid 2 -...

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EECS 141: SPRING 02 – MIDTERM 2 University of California College of Engineering Department of Electrical Engineering and Computer Science Jan M. Rabaey TuTh 2:00-3:30 pm Andrei Vladimirescu [email protected]

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PROBLEM 1: Logic Design For the gate shown below assume that - each NMOS drain or source contributes 1 fF from the node it is connected to ground; - each PMOS drain or source contributes 3fF from the node it is connected to ground; - the ON resistance of the NMOS equals that of the PMOS and is 10k a) Attach the capacitance at each node in the diagram (rejoice: this is a freebie). b) Find the Ellmore delay when the inputs abcd are initially 1010 and then a switches 1->0. Make sure to draw the equivalent circuit diagram you are using. Hint: “if an intermediate capacitance is already precharged to the correct value, assume that this capacitor contributes nothing to the Ellmore delay, and can hence be ignored in the model.”
c) Find the Ellmore delay when the inputs abcd are 1000 and then c switches 0->1

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Electrical Engineering 141 - Spring 2002 - Rabaey - Mid 2 -...

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