lec12 - ENGR 111 Lecture 12 Reading: Chapters 22, 27 Class...

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ENGR 111 Lecture 12 Reading: Chapters 22, 27 Class notes
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Review of last lecture z Truth table –complete representation { Simple method for checking logic equivalence { Allow sum-of-products logic realization z Logic gates are used to build circuits z Basic logic rules allow logic simplification { Reduces the circuit complexity z Combinational circuits –no memory z Today’s lecture – memory elements
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SR latch
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SR latch z The current output depends on previous state (for inputs 11) z Remembers old state
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Transparent latch z Only allows SR inputs that differ z When Enable = 1, Q = D, else Q(new) = Q(old)
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Master-slave flip-flop
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Master-slave of D flip-flop z Has two stages z The first half active when clock is 0 z The second half active when clock is 1 z The input D gets transferred to output Q on rising edge of clock { Output transitions happen on clock boundaries { Allows predictable behavior without races
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D flip-flops in series z Each rising edge input is reflected at the next output z Allows data to be remembered for longer time Input D(t) D(t-1) D(t-2) Clock
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lec12 - ENGR 111 Lecture 12 Reading: Chapters 22, 27 Class...

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