ADL_HW3 ShihChe.pdf - EEDG/CE 6301:Advanced Digital Logic...

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EEDG/CE 6301:Advanced Digital Logic HW #3 Shih-Che Chen 2021190145
HW#3 Problem 2 1.HDL description module hw3_q2(fc, b,l); input [2:1]fc; //f means fault signal, c means control signal output b,l; //b=1 buzzer ON , //l=0 green light ON, red light OFF //l=1 green light OFF, red light ON reg b,l; reg [3:1]Y; //next stage reg [3:1]y; parameter [3:1]s0=3'b000, s1=3'b001, s2=3'b011, s3=3'b010, s4=3'b110, s5=3'b111; [email protected](fc or y ) begin case (y) s0:if(fc==2'b00) Y=s0; else if(fc==2'b01) Y=s1; else if(fc==2'b10) Y=s3; s1:if(fc==2'b00) Y=s0; else if(fc==2'b01) Y=s1; else if(fc==2'b11) Y=s2; s2:if(fc==2'b11) Y=s2; else if(fc==2'b10) Y=s3; s3:if(fc==2'b11) Y=s4; else if(fc==2'b10) Y=s3; s4:if(fc==2'b01) Y=s1; else if(fc==2'b11) Y=s4; else if(fc==2'b10) Y=s5; s5:if(fc==2'b00) Y=s0; else if(fc==2'b11) Y=s4; else if(fc==2'b10) Y=s5; default: Y=3'b000; endcase y<=Y; b=(y==s2)+(y==s3); l=(y==s2)+(y==s3)+(y==s4)+(y==s5); end endmodule

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