adl_hw5_q1.pdf - HW#5-Problem1 Synthesis Algorithm for...

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HW#5-Problem1 Synthesis Algorithm for Application- Specific Homogeneous Processor Networks Jason Cong, Fellow, IEEE, Karthik Gururaj, Guoling Han, and Wei Jiang 1. Basic problem A. System model In this paper, they aim to the architecture template of homogeneous processors connected by point-to-point FIFOs (as illustrated by an example in Fig. 1). This simple model is accurate enough to capture the point-to-point FIFO communications, but it is quite easy to replace it with other models that reflect the target architecture. B. Homogeneous ASPN Synthesis Problem The stage period T is defined as the reciprocal of the throughput. The application latency is defined as the elapsed time from the data input streams to the output streams. A task graph G(V,E) with profiling inf ormation, user- specified throughput constraint, construct a homogeneous ASPN system by (1) partitioning the tasks into convex clusters, ( 2) mapping the clusters onto the processors and inter-processor communication to FIFOs.

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