sol7 - Chapter 7 7.1. Clock D Qa Qb Qc 7.2. The circuit in...

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Chapter 7 7.1. D Clock Qa Qb Qc 7.2. The circuit in Figure 7.3 can be modified to implement an SR latch by connecting S to the Data input and S + R to the Load input. Thus the value of S is loaded into the latch whenever either S or R is asserted. Care must be taken to ensure that the Data signal remains stable while the Load signal is asserted. 7.3. S RQ a Q b 11 10 01 00 0/1 1/0 S (no change) Q a Q b R 7.4. S R Clk Q Q 7-1
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7.5. T Q Q 100 MHz T Q Q T Q Q 1 50 MHz 25 MHz 12.5 MHz 100 MHz 50 MHz 25 MHz 12.5 MHz 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns 70 ns 7.6. D Q Q Q Q S Clock SQ Q R 0 1 Q t 1 + () Q t 0 S 0 0 0 1 1 1 0 1 R R 7-2
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7.7. Q Q S R 7.8. T Q Q Q Q J Clock K 7.9. This circuit acts as a negative-edge-triggered JK flip-flop, in which J = A,K = B, Clock = C, Q= D, and E . This circuit is found in the standard chip called 74LS107A (plus a Clear input, which is not shown). 7-3
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7.10. module tflipflop (T, Clock, Resetn, Q); input T, Clock, Resetn; output Q; reg Q; always @( negedge Resetn or posedge Clock) if (!Resetn) Q < =0; else if (T) Q < =Q ; endmodule 7.11. module jkflipflop (J, K, Clock, Resetn, Q); input J, K, Clock, Resetn; output Q; reg Q; always @( negedge Resetn or posedge Clock) if (!Resetn) Q < else case (J, K) 1’b01: Q < 1’b10: Q < =1; 1’b11: Q < ; default :Q < =Q; endcase endmodule 7.13. Let S = s 1 s 0 be a binary number that specifies the number of bit-positions by which to rotate. Also let L be a parallel-load input, and let R = r 0 r 1 r 2 r 3 be parallel data. If the inputs to the flip-flops are d 0 ...d 3 and the outputs are q 0 ...q 3 , then the barrel-shifter can be represented by the logic expressions d 0 = L · r 0 + L · ( s 1 s 0 q 0 + s 1 s 0 q 3 + s 1 s 0 q 2 + s 1 s 0 q 1 ) d 1 = L · r 1 + L · ( s 1 s 0 q 1 + s 1 s 0 q 0 + s 1 s 0 q 3 + s 1 s 0 q 2 ) d 2 = L · r 2 + L · ( s
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sol7 - Chapter 7 7.1. Clock D Qa Qb Qc 7.2. The circuit in...

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