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# sol10 - Chapter 10 10.1 In the modified shift register the...

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Chapter 10 10.1. In the modified shift register the order of the multiplexers that perform the load and enable operations are reversed from the order in Figure 10.4. Bit zero of the modified register is show below. D Q Q Q 0 R 0 Clock E 1 0 w L 1 0 10.2. ( a ) A modified ASM chart that has only Moore-type outputs in state S2 is given below. Shift A Done A 0? = B 0 s Load A a 0 Reset S4 0 1 0 1 0 1 s B B 1 + Shift A S1 S2 S3 1 0 10-1

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( b ) EA Done = 1 z s a 0 Reset S4 0 1 0 1 0 1 s EA, EB S1 S2 S3 LB 1 0 10-2
( c ) module bitcount (Clock, Resetn, LA, s, Data, B, Done); input Clock, Resetn, LA, s; input [7:0] Data; output [3:0] B; output Done; wire [7:0] A; wire z; reg [1:0] Y, y; reg [3:0] B; reg Done, EA, EB, LB; // control circuit parameter S1 = 2’b00, S2 = 2’b01, S3 = 2’b10, S4 = 2’b11; always @(s or y or z) begin : State table case (y) S1: if (s == 0) Y = S1; else Y = S2; S2,S3: if (!z && !A[0]) Y = S2; else if (!z && A[0]) Y = S3; else Y = S4; S4: if (s == 1) Y = S4; else Y = S1; endcase end always @( posedge Clock or negedge Resetn) begin : State flipflops if (Resetn == 0) y < = S1; else y < = Y; end always @(y or A[0]) begin : FSM outputs EA = 0; LB = 0; EB = 0; Done = 0; // defaults case (y) S1: LB = 1; S2: EA = 1; S3: begin EA = 1; EB = 1; end S4: Done = 1; endcase end 10-3

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// datapath circuit // counter B always @( negedge Resetn or posedge Clock) if (!Resetn) B < = 0; else if (LB) B < = 0; else if (EB) B < = B + 1; shiftrne ShiftA (Data, LA, EA, 0, Clock, A); assign z = ∼| A; endmodule 10.3. ( a ) Done P P A + C n 1? = P 0 C 0 , s Load A b C Reset S3 0 1 0 1 0 1 s S1 S2 1 0 Load B Shift left A, C C 1 + 10-4
( b ) E L E 0 DataA LA EA A Clock P 2 n DataP 2 n register EP Sum 2 n 2 n 0 B n DataB LB 2 n + L E Counter . C 0 LC EC Psel E Register b C z n-to-1 Shift-left log 2 n ( c ) The ASM chart for the control circuit is shown below. Note that we assume the EB signal is controlled by external logic. 10-5

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EP z b C Reset S3 0 1 0 1 s 0 1 Done Psel 0 = EP, LC , s 0 1 S1 S2 Psel 1 = EA EC , , ( d ) module multiply (Clock, Resetn, LA, LB, s, DataA, DataB, P, Done); parameter n = 8; parameter m = 3; input Clock, Resetn, LA, LB, s; input [n - 1:0] DataA, DataB; output [n+n - 1:0] P; output Done; wire bc, z; reg [n+n - 1:0] DataP; wire [n+n - 1:0] A, Sum; reg [1:0] y, Y; wire [n - 1:0] B; wire [m - 1:0] C; reg Done, EA, EP, Psel, LC, EC; integer k; 10-6
// control circuit parameter S1 = 2’b00, S2 = 2’b01, S3 = 2’b10; always @(s or y or z) begin : State table case (y) S1: if (s == 0) Y = S1; else Y = S2; S2: if (z) Y = S3; else Y = S2; S3: if (s == 1) Y = S3; else Y = S1; default : Y = 2’bxx; endcase end always @( posedge Clock or negedge Resetn) begin : State flipflops if (Resetn == 0) y < = S1; else y < = Y; end always @(y or bc) begin : FSM outputs EA = 0; EP = 0; Done = 0; Psel = 0; EC = 0; LC = 0; // defaults case (y) S1: begin EP = 1; EC = 1; LC = 1; end S2: begin EA = 1; Psel = 1; EC = 1; LC = 0; if (bc) EP = 1; else EP = 0; end S3: Done = 1; endcase end // datapath circuit regne RegB (DataB, Clock, Resetn, LB, B); defparam RegB.n = 8; shiftlne ShiftA ( {{ n { 1’b0 }} , DataA } , LA, EA, Clock, A); defparam ShiftA.n = 16; upcount Counter (LC, Clock, EC, C); defparam Counter.n = m; 10-7

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assign bc = B[C]; assign z = &C; assign Sum = A + P; // define the 2n 2-to-1 multiplexers always @(Psel or Sum) for (k = 0; k < n+n; k = k+1) DataP[k] = Psel ? Sum[k] : 0; regne RegP (DataP, Clock, Resetn, EP, P); defparam RegP.n = 16; endmodule 10.4.
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sol10 - Chapter 10 10.1 In the modified shift register the...

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