hw1.docx - EEDG 6301 Advanced Digital Logic Homework 1 Siddhartha Regmi Due date Report Area dc_shell> report_area Information Updating design

hw1.docx - EEDG 6301 Advanced Digital Logic Homework 1...

This preview shows page 1 - 8 out of 25 pages.

EEDG 6301:Advanced DigitalLogicHomework # 1Siddhartha RegmiDue date: 09/06/2018
Report Areadc_shell> report_areaInformation: Updating design information... (UID-85)****************************************Report : areaDesign : minimizationVersion: B-2008.09-SP2Date : Thu Sep 6 00:34:50 2018****************************************Library(s) Used:class (File: /home/cad/synopsys_2007.12/syn/libraries/syn/class.db)
Number of ports: 5Number of nets: 10Number of cells: 6Number of references: 4Combinational area: 11.000000Noncombinational area: 0.000000Net Interconnect area: undefined (Wire load has zero net area)Total cell area: 11.000000Total area: undefinedReport powerdc_shell> report_powerWarning: Main library 'class' does not specify the following unit required for power: 'Leakage Power'. (PWR-424)Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)Warning: There is no defined clock in the design. (PWR-80)Warning: Design has unannotated primary inputs. (PWR-414)****************************************
Report : power-analysis_effort lowDesign : minimizationVersion: B-2008.09-SP2Date : Thu Sep 6 00:35:59 2018****************************************Library(s) Used:class (File: /home/cad/synopsys_2007.12/syn/libraries/syn/class.db)Information: The cells in your design are not characterized for internal power. (PWR-229)Operating Conditions: Wire Load Model Mode: topDesign Wire Load Model Library------------------------------------------------minimization 05x05 classGlobal Operating Voltage = 5 Power-specific unit information :Voltage Units = 1VCapacitance Units = 0.100000ffTime Units = 1nsDynamic Power Units = 100nW (derived from V,C,T units)Leakage Power Units = UnitlessCell Internal Power = 0.0000 nW (0%)Net Switching Power = 1.8416 uW (100%)---------Total Dynamic Power = 1.8416 uW (100%)Cell Leakage Power = 0.0000Report timing dc_shell> report_timing****************************************
Report : timing-path full-delay max-max_paths 1Design : minimizationVersion: B-2008.09-SP2Date : Thu Sep 6 00:36:36 2018****************************************Operating Conditions: Wire Load Model Mode: topStartpoint: b (input port)Endpoint: f (output port)Path Group: (none)Path Type: maxDes/Clust/Port Wire Load Model Library------------------------------------------------minimization 05x05 classPoint Incr Path----------------------------------------------------------- input external delay 0.00 0.00 rb (in) 0.00 0.00 rU11/Z (IV) 0.36 0.36 fU10/Z (NR2) 1.17 1.53 rU9/Z (MUX21L) 0.49 2.02 fU8/Z (MUX21L) 0.39 2.41 rf (out) 0.002.41 rdata arrival time 2.41-----------------------------------------------------------(Path is unconstrained)
Minimization.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity minimization is port (a, b, c, d : in std_logic;f : out std_logic);end minimization;architecture minimization_arch of minimization issignal tmp : std_logic_vector (3 downto 0);begintmp<= a&b&c&d;with tmp selectf <= '1' when "0011"| "0110"|"1011"|"1101",'0' when others;end minimization_arch;Tbminimization.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity tbminimization isend tbminimization;architecture tbminimization_arch of tbminimization iscomponent minimization port ( a, b, c, d : in std_logic;f: out std_logic);end component;signal in_A, in_B, in_C, in_D, out_f:std_logic:='0';begin
inminimization : minimization port map (a => in_A,b => in_B, c => in_C,d => in_D, f => out_f);process beginin_A <='0'; in_B<='0'; in_C<= '0'; in_D<='0';wait for 10 ns;in_A <='0'; in_B<='0'; in_C<= '0'; in_D<='1';wait for 10 ns;in_A <='0'; in_B<='0'; in_C<= '1'; in_D<='0';wait for 10 ns;in_A <='0'; in_B<='0'; in_C<= '1'; in_D<='1';

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture