16 bit Signed Multiplier

16 bit Signed Multiplier - 16 bit Signed Multiplier 282X...

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16 bit Signed Multiplier 282X Lab Project Brad Smith In this project, we were given a layout for a 16 bit signed Multiplier, and were supposed to put it together in both Verilog HDL and Block Schematic format. The Multiplier was to consist of 1 7 bit counter, 1 Control, 1 16x16 Registerfile, 1 16 bit ALU, 1 16 bit shifter, and 1 16 bit 4 to 1 MUX. The Register file, ALU, and Shifter were all done at previous times and will be discussed later, while the counter, control, and MUX were designed specifically for the project. With the way these modules are positioned on the data path, it allows the counter to dictate which step in the process of multiplying the Multiplier is at, which tells the control what signals to send out so that the register, ALU, Shifter, and MUX can do their jobs in completing the process. The overall data path, or the connection between the modules, is very straight forward, it’s the processes within that are a bit more complicated. Since we had already created several of the components in previous labs, I will focus mainly on the components we were to build specifically for this project. The first and simplest one was the 16 bit 4 to 1 MUX. Our already created 4 to 1 MUX was made only for 1 bit or 2 bit inputs, so we had to go within and spread the input and output width so that it could accommodate a 16 bit input rather then the smaller ones. Since our 4 to 1 MUX is built off 2 to 1 MUXes, we had to step back and change them as well, until everything was the proper size. The next thing we needed to create was a counter to designate which states we were at. While we had studied counters in lecture, we never actually built one within lab,
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so we couldn’t simply pull one out of nowhere. We were going to do it in Block Schematic format, but decided on Verilog instead, as we can achieve the same objective, but we could do it quicker with Verilog. Creating a counter in Verilog is simply by using a couple if statements. If the reset is on, set the counter to zero. Else, if the enable is on, add 1 bit to the current result, where the result starts initially at zero. By making result only 7 bits, as was our goal, this keeps it limited to 127 steps, but we only need 68 of them. Giving it the clock to run off to, the enable, and the reset, and having the output be
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