homework2 - Homework 2 CPRE 488X, Embedded Systems Design,...

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Homework 2 CPRE 488X, Embedded Systems Design, Fall 2006 Due: Monday Sept. 18 on WebCT Name: Brad Smith Lab Section: Tuesday 6-9 Search the Internet for the answers to questions 1-2. Other questions are from textbook pages 174-176 and 446-447. 1. [10] Give short answers to the following questions about the PowerPC 405 CPU core, which is used in the XUP FPGA board. Specify the source you used (like web URL, document title, publisher and/or year of publish.) a. What is the frequency range of the PowerPC 405 core? 250 – 400 mhz http://www-03.ibm.com/chips/power/powerpc/cores/ppc405.html b. What memories, including caches, are provided with the core? 6 KB 2-way set-associative instruction and data caches http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/ virtex_ii_pro_fpgas/capabilities/powerpc.htm c. How much is its max power dissipation? In comparison, find out the max power dissipation of a current Intel or AMD processor used for desktop/notebook computers. <1.5W maximum for Core http://www.amcc.com/webdev/Stage/Embedded/PPC405EZ_PB_1_15.pdf#se arch=%22max%20Power%20Dissipation%20PowerPC%20405%20core%22 300-400W for AMD processor http://www.tomshardware.com/2000/10/17/amd_extends_performance_lead_with _new_athlon_and_duron_processor/index.html
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2. [10] Describe the pipeline organization of the PowerPC 405 core, including
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This note was uploaded on 03/27/2008 for the course CPRE 488X taught by Professor Zhang during the Spring '08 term at Iowa State.

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homework2 - Homework 2 CPRE 488X, Embedded Systems Design,...

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