homework4 - CprE 488 Embedded Systems Design Homework 4,...

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CprE 488 Embedded Systems Design Homework 4, Fall 2005 Name: Brad Smith Lab Section: Tuesday 6-9 1. [10] Q3-25. Assume that a system has a two-level cache: The level 1 cache has a hit rate of 90% and the level 2 cache has a hit rate of 97%. The level 1 cache access time is 4ns, the level 2 access is 15ns, and the main memory access time is 80ns. What is the average memory access time? =0.9*4+(.07)*15+(.03)*80 =3.6+1.05+2.4 =7.05 ns
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2. [20] Q3-26. In the two-way set-associative cache with four sets of Example 3-9, show the state of the cache after each memory access, as was done for the direct- mapped cache. Use the LRU replacement policy.
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3. [10] What is VLIW? Why is the VLIW architecture a good choice for embedded processors designed for media (audio and video) processing? What is the major disadvantage of using VILW? Very Long Instruction Word, This architecture decides in software how the instructions for the processor are going to proceed. It can move and preschedule operations so that the work and the hardware is not nearly as complicated. This
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This note was uploaded on 03/27/2008 for the course CPRE 488X taught by Professor Zhang during the Spring '08 term at Iowa State.

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homework4 - CprE 488 Embedded Systems Design Homework 4,...

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