Tessent IJTAG User\u2019s Manual.pdf - Tessent IJTAG Users Manual Software Version 2018.1 March 2018 Document Revision 8 2012-2018 Mentor Graphics

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Unformatted text preview: Tessent® IJTAG User’s Manual Software Version 2018.1 March 2018 Document Revision 8 © 2012-2018 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. Note - Viewing PDF files within a web browser causes some links not to function (see MG595892). Use HTML for full navigation. This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a thirdparty Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’ trademarks may be viewed at: mentor.com/trademarks. The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of Linus Torvalds, owner of the mark on a world-wide basis. End-User License Agreement: You can print a copy of the End-User License Agreement from: mentor.com/eula. Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777 Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: mentor.com Support Center: support.mentor.com Send Feedback on Documentation: support.mentor.com/doc_feedback_form Revision History Revision Changes Status/ Date 8 Modifications to improve the readability and comprehension of the content. Approved by Lucille Woo. All technical enhancements, changes, and fixes listed in the Tessent Release Notes for this product are reflected in this document. Approved by Ron Press. Released Mar 2018 7 Modifications to improve the readability and comprehension of the content. Approved by Lucille Woo. All technical enhancements, changes, and fixes listed in the Tessent Release Notes for this product are reflected in this document. Approved by Ron Press. Released Dec 2017 6 Modifications to improve the readability and comprehension of the content. Approved by Lucille Woo. All technical enhancements, changes, and fixes listed in the Tessent Release Notes for this product are reflected in this document. Approved by Ron Press. Released Sep 2017 5 Modifications to improve the readability and comprehension of the content. Approved by Lucille Woo. All technical enhancements, changes, and fixes listed in the Tessent Release Notes for this product are reflected in this document. Approved by Ron Press. Released Jun 2017 Author: In-house procedures and working practices require multiple authors for documents. All associated authors for each topic within this document are tracked within the Mentor Graphics Technical Publication’s source. For specific topic authors, contact Mentor Graphics Technical Publication department. Revision History: Released documents maintain a revision history of up to four revisions. For earlier revision history, refer to earlier releases of documentation which are available at the following URL: Tessent® IJTAG User’s Manual, v2018.1 March 2018 Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation. 4 Tessent® IJTAG User’s Manual, v2018.1 March 2018 Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation. Table of Contents Revision History Chapter 1 Introduction to Tessent IJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tessent IJTAG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL and PDL Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . License Usage/Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 16 17 Chapter 2 ICL and PDL Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Instrument Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Build an ICL Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Model Global Reset, Local Reset and Embedded TAPs . . . . . . . . . . . . . . . . . . . . . How to Define an iProc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Call an iProc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 23 33 34 Chapter 3 A Typical PDL Retargeting Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Basic PDL Retargeting Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoke Tessent Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set the IJTAG Context and System Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read ICL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read PDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set the Retargeting Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Define Clocks and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Rule Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Create Pattern Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write PDL, Pattern, and Test Bench Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit the Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Elements of a PDL Retargeting Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Setup and Test End Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Define and Use Clocks Outside ICL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Constrain Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IJTAG Introspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Run iCalls in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDL Specialties and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iMerge Conflict Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDL Retargeting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 38 38 39 39 41 41 42 43 44 44 47 48 49 49 50 50 51 52 56 57 57 63 Tessent® IJTAG User’s Manual, v2018.1 March 2018 5 Table of Contents Introspection and Reporting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Chapter 4 ICL Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Required Inputs for ICL Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Inputs for ICL Extraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing ICL Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Down and Bottom-Up ICL Extraction Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Down ICL Extraction Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom-Up ICL Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Extraction Design Rule Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging DRC Violations with DFTVisualizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Influence the ICL Extraction Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Influence ICL Extraction through Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Influence ICL Extraction Through ICL Module Attributes. . . . . . . . . . . . . . . . . . ICL Network Extraction of Parameterized Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Extraction Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 71 72 72 72 75 76 77 78 79 80 80 84 87 88 Chapter 5 IJTAG Network Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The IJTAG Network Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IJTAG Network Insertion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modification of the IJTAG Network Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Edit or Modify a DftSpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DftSpecification Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 92 93 94 96 98 98 Chapter 6 IJTAG and ATPG in Tessent Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IJTAG ATPG Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IJTAG Features of ATPG in Tessent Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDT IP Setup for IJTAG Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Set Up Embedded Instruments Through Test Procedures . . . . . . . . . . . . . . . . . . . How to Set Up Embedded Instruments Through the Dofile. . . . . . . . . . . . . . . . . . . . . . . . Implicit and Explicit iReset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Detailed IJTAG ATPG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 109 111 111 113 114 115 117 Chapter 7 IJTAG Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Modeling versus Verilog Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Namespaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDL Namespaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Define Default Values in ICL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes of the ICL Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Chain Integrity Test in Tessent IJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Define Auto-Return Values in ICL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Model Addressable Registers in ICL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 122 123 124 124 126 127 128 130 6 Tessent® IJTAG User’s Manual, v2018.1 March 2018 Table of Contents Chapter 8 Verification and Debug of IJTAG Instruments and Networks . . . . . . . . . . . . . . . . . . . . . General Guidelines for Debugging Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating ICL Verification Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using ICL Verification Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICL Verification Patterns Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Displaying the Comparison Failure Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 136 136 136 140 140 141 Appendix A Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 The Tessent Documentation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Mentor Support Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Third-Party Information End-User License Agreement Tessent® IJTAG User’s Manual, v2018.1 March 2018 7 Table of Contents 8 Tessent® IJTAG User’s Manual, v2018.1 March 2018 List of Figures Figure 1-1. IJTAG High-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 1-2. Tessent IJTAG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-1. Example ICL Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-2. Association Between ResetPorts and Registers . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-3. Hierarchical Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-4. Modeling Self-clearing Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-1. PDL Retargeting Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-2. First Pattern Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-3. First and Second Pattern Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-4. Pattern Set Report with Two Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-5. iMerge Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-1. Generic ICL Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-2. ICL Rule Violation Debug in DFTVisualizer. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-3. Logical Connection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5-1. IJTAG Network Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5-2. Configuration Data Window for DftSpecification . . . . . . . . . . . . . . . . . . . . . . . Figure 7-1. Gate-Level Verilog Module Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-2. Schematic View of an Indirect Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . Figure 7-3. ICL Description of an Indirect Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . Figure 8-1. Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tessent® IJTAG User’s Manual, v2018.1 March 2018 13 14 21 27 28 30 36 46 46 52 62 71 79 82 92 96 122 131 132 138 9 List of Figures 10 Tessent® IJTAG User’s Manual, v2018.1 March 2018 List of Tables Table 1-1. Tessent IJTAG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3-1. Conflict Report Teminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 3-2. PDL Retargeting Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 3-3. ICL Introspection and Reporting Command Summary . . . . . . . . . . . . . . . . . . . 65 Table 4-1. Values for ICL Extraction Attribute connection_rule_option . . . . . . . . . . . . . 85 Table 4-2. ICL Extraction Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 5-1. Modifications to the IJTAG Network Insertion Flow . . . . . . . . . . . . . . . . . . . . . 94 Table 5-2. IJTAG Network Insertion Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 6-1. EDT Configuration Keywords and Values . . . . . . . . . ...
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