hw4.pdf - EE271 Problem Set 4 This homework is due on Thursday October 25 Unless otherwise specified please use the values below where needed • � =

# hw4.pdf - EE271 Problem Set 4 This homework is due on...

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1 EE271 Problem Set 4 This homework is due on Thursday, October 25 Unless otherwise specified, please use the values below where needed: λ = 0.0225 μmRsqp= 24 kΩ/squareRsqn= 12 kΩ/squareCgate= 1.2 fF per μm of WCdiff= 1.2 fF per μm of WVDD= 1V By default, all transistors are minimum length (2λ)By default, there is zero clock skew unless otherwise specified Clock Skew Clock skew is the delay between the clock edges. As the clk signal propagates downstream, it accumulates delay due to RC of the wire and due to gate delay when clocks are gated. Positive clock skew means that blocks later in the chain receive the clock edge later. (Look at slides 32-35 for more info.) 1. Edge-Triggered Clocking (25 points) The system below contains two edge-triggered flip-flops connected by some combinational logic: Flip-Flop 1, Flip-Flop 2 Combinational Logic 1 Combinational Logic 2 tsetup= 0.5ns thold= 0.4ns tc-q= 0.8ns Td,min= 3ns Td,max= 8ns Td,min= 2ns Td,max= 11ns a. Assuming zero clock skew, what is the minimum clock period? b. Given the clock period found in part (a), explain whether the system would work for each of the following scenarios. If not, how could we change the clock period to meet timing?  • • • 