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Unformatted text preview: Name:____SOLUTION___ Page 1 of 10 CS/ECE 552 Introduction to Computer Architecture Midterm Exam Wednesday, October 25, 1995 7:15-9:15 p.m Name:_________________SOLUTION____________________________________ Limit your answers to the space provided. Unnecessarily long answers will be penalized. If you use more space than is provided, you are probably doing something wrong. Use the back of each page for any scratch work. Write your last name on each page. Problem 1. Problem 2. Problem 3. Problem 4. Problem 5. Problem 6. Total ______________ (out of 20 points) ______________ (out of 16 points) ______________ (out of 8 points) ______________ (out of 16 points) ______________ (out of 16 points) ______________ (out of 24 points) ______________ (out of 100 points) Name:____SOLUTION___ Page 2 of 10 (1) Lookahead Incrementer Design (20 points) The following is a typical arrangement for a 4-bit adder designed with a carry lookahead (CLA) unit. P G CLA p3 g3 p2 g2 p1 g1 p0 g0 FA C3 FA C2 FA C1 FA C0 S3 A3 B3 S2 A2 B2 S1 A1 B1 S0 A0 B0 (i) If the circuit is to be used only as an incrementer, i.e., to add 1 to an input A, what are the logic equations for the following signals: (Hint: the equations are simpler than the corresponding equations for an adder). (6 points) g3 = p3 = P= G= 0 A3 p3p2p1p0 0 (ii) Give the design of the FA and CLA boxes of the incrementer using AND, OR, and NOT gates. In your design, show only those signals that are relevant to the incrementer. (6 points) FA Box: generates pi = Ai, Si = AiCi + AiCi CLA Box: generates Pi = p0p1p2p3, C1 = p0C0, C2 = p0p1C0, C3 = p0p1p2C0 ¢ ¡ (iii) Using the FA and the CLA blocks designed for the incrementer, describe how you could realize a 16-bit incrementer (either using words or by sketching the design on the facing page). How many gate delays does it take from the time that all input bits for A are available until the sum bit S15 is ready. Show your work. (8 points) Take 16 1-bit incrementer units, and 5 CLA units. Make a 2-level tree with the CLA units, connecting the Pi from the first level to the p inputs at the second level. Make C0=1. The total delay through the incrementer is 5d, which is 1d going up the first level of the CLA, 1d at the 2nd level, 1d coming down the first level of the CLA, and 2d in the FA units to arrive at the final sum bits. Name:____SOLUTION___ Page 3 of 10 (2) Microprogrammed Control (16 points) In this problem, you are to use microprogrammed control to implement a finite-state machine (FSM) for a control circuit, in manner similar to how the control FSM is implemented in the book. The control circuit has two 1-bit inputs x and y, and five 1-bit outputs, z 0 , z 1 , z 2 , z 3 and z 4 . zi = 1 if the machine is in state si, and 0 otherwise. The finite-state machine describing the control circuit is shown in the figure below. S0 x=0 or 1 x=1 x=0 x=0 S1 x=0 or 1 S2 x=1, y=1 x=0 x=1, y=0 S3 x=1, y=0 S4 x=1, y=1 The microinstruction format you are to use is: ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢¢ ¡¡¡¡¡¡¡¡¡¡¢¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¢¢ ¢¢ ¢¢ z0 z1 z2 z3 z4 Next_Addr_Mean 1-bit Next_Addr 3-bits 1-bit 1-bit 1-bit 1-bit 1-bit The fields of the microinstruction are: (i) z 0 , z 1 , z 2 , z 3 , and z 4 are the bits representing the outputs of the control circuit, (ii) Next_Addr_Mean, and (iii) Next_Addr. The Next_Addr_Mean indicates how the next address generation logic should use the bits of the Next_Addr field. Specifically, if Next_Addr_Mean = 0 the 3 bits of the Next_Addr field should be used as the address of the next microinstruction. If Next_Addr_Mean = 1 the 3 bits of the Next_Addr field should be used as the number of a dispatch ROM, and the ROM provides the address of the next microinstruction. Fill in the table on the next page with your microprogram and fill in the contents of the dispatch ROMs in the figure below the table. ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¢ ¢ ¢ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¢ ¡¡¡ ¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡ ¢ Name:____SOLUTION___ Microinstruction Address 111 110 101 100 011 010 001 000 z0 0 0 0 0 1 z1 0 0 0 1 0 z2 0 0 1 0 0 z3 0 1 0 0 0 Microinstruction z4 1 0 0 0 0 Next_Addr_Mean 1 0 1 0 1 Next_Addr Page 4 of 10 011 000 010 000 001 Address 00 01 10 11 ROM1 001 001 010 010 Data Address 00 01 10 11 X ROM2 ROM 010 010 011 100 Y Data Address Data Address 00 01 10 11 ROM3 100 100 011 000 Data Name:____SOLUTION___ Page 5 of 10 (3) Machine Performance (8 points) Consider two machines, machine A and machine B. Machine B runs floating-point instructions 5 times faster than machine A. (i) Consider a program that takes 10 seconds to run on machine A, and spends half its time in floating-point instructions. How much faster is machine B (over machine A) at executing this program? (4 points) Time on B = 5 + 5/5 = 6 secs. So B is 10/6 or 1.67 times faster. (ii) Suppose we want a benchmark program to run 3 times faster on machine B than it runs on machine A. What fraction of its time does it spend executing floating point instructions on machine A? What fraction of its time does the same program spend executing floating-point instructions on machine B? (4 points) Let X be fraction of time executing floating point on machine A. Time on machine B = X/5 + (1-X) = 1/3. Solve for X to get X = 5/6. So machine A spends 5/6 of its time in floating point instructions. Similarly, Machine B spends 1/2 its time executing floating point. Name:____SOLUTION___ Page 6 of 10 (4) (i) Short Questions (16 points) Write the formula for determining the execution time of a program. (4 points) Time for program = number of instructions × cycles per instruction × clock cycle time (ii) Many modern processors have 5 or 6 stage pipelines. A typical value for the CPI (cycles per instruction) in such processors is in the range of 1.0 to 1.5. Does it mean that the latency of execution of most instruction 1 or 2 clock cycles? Why, or why not? (4 points) No. CPI is a measure of throughput, i.e., an instruction is being executed every 1.0 to 1.5 clock cycles. Because of pipelining, more than one instruction is in execution in the processor, and the latency of the instruction is the amount of time taken to go through all the (5 or 6) stages of the pipeline. (iii) In the MIPS instruction set, the top 6 bits (bits 31..26) are reserved for an opcode. With 6 bits, we can have 64 different combinations. Does this mean that the total number of instructions in the MIPS instruction set is less than 64? Explain. (4 points) No. One (or more) of these combinations is used to indicate that some other bits of the instruction contain opcode information. For example, in the R-Type format, the funct field is used to specify the ALU instruction. (iv) Give two ways of reducing the performance degradation due to branch hazards, with a short description of each way. (4 points) (1) Move up the branch determination point in the pipeline (say to the EX stage) so that branches are resolved earlier. (2) Continue executing branches from th enot taken path, and squash such instructions in case the branch is taken. (3) Delayed branches. Change the semantics of the branch to (unconditionally) execute an instruction after the branch. ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ Cycles 1 2 3 4 5 6 7 8 9 10 11 IF ADD LOAD1 LOAD2 LOAD2 SUB SUB r1 <- r1 + r2 load r2 <- mem(r1) load r3 <- mem(r2) r4 <- r1 - r2 ADD LOAD1 LOAD1 LOAD2 LOAD2 SUB ID ADD bubble LOAD1 bubble LOAD2 SUB EX bypass (b) (a) Name:____SOLUTION___ (5) For the following instruction sequence, show the pipeline timing in the table. Part of the timing for the first instruction is shown. (12 points) What purpose does the bypass serve? (4 points) Pipelining (16 points) Following is a simple pipeline; with a bypass from the output of the MEM stage to the EX stage. (Note: There is no bypass from the EX stage back to the EX stage.) Assume that the register file is written in the first half and read in the second half of the clock cycle. Hence, a register value can be written and read in the same cycle. Stall Memory Inst IF insert 0s Hazard Detect Reg. File ID ALU EX ADD LOAD1 LOAD2 SUB Mem Data MEM ADD bubble LOAD1 bubble LOAD2 SUB MEM ADD bubble LOAD1 bubble LOAD2 SUB WB Reg. File WB Page 7 of 10 Name:____SOLUTION___ Page 8 of 10 (6) Datapath (24 points) Consider the datapath shown in figure 1. It is almost the same as the one in the H&P textbook for the multicycle implementation. The main difference is that there is the option to specify register 31 as the target register during write to the registers, and the addition of extra control signals, interconnections, and logic. The actions corresponding to the values of the control signals are as follows (IR is used in place of "Instruction Register"): ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¢ ¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ Signal MemRd MemWr ALUSelA RegWrite Action if deasserted (0) None None PC is the first ALU operand None ZeroEnCond IorD IRWrite RegWrite signal passes to WriteEnable pin of Registers. PC supplies the address to memory None None None PCWrite TargetWrite Action if asserted (1) Memdata <- Memory[Read Address] Memory[Write Address] <- Write Data The register whose number is given by bits [25-21] of the instruction register is the first ALU operand Register[Write Register] <- Write data, if the output of the nand gate is 1. RegWrite signal passes to WriteEnable pin of Registers if Zero is inactive. ALU output is the address supplied to memory The value from memory (MemData) is written into the Instruction register (IR) PC is written; PCSource controls the input Target buffer gets written. Table 1. 1-bit control lines and their actions ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ Signal ALUSeIB ALUOp WritedataSel Value 0 1 2 3 0 1 2 0 1 2 3 0 1 2 0 1 2 3 RegDst PCSource Action Second ALU input is the register given by bits [25-21] of IR. Second ALU input is the register given by the bits [20-16] of IR Second ALU input is 4 Second ALU input is the lower 16 bits of IR sign-extended to 32 bits ALU does an add ALU does a subtract ALU does an OR. The value fed to the registers as write data, comes from the memory The value fed to the registers as write data, comes from the ALU output The value fed to the registers as write data, comes from the register given by bits [20-16] of IR. The value fed to the registers as write data, comes from the PC output. Bits [20-16] of IR specify which register is going to be written if WriteEnable is active Register 31 gets written if WriteEnable is active Bits [15-11] of IR specify which register is going to be written is WriteEnable is active Value stored in Target is sent to PC. Output of ALU is sent to PC. Bits [25-0] from IR left shifted by 2 with bits [31-28] from the PC concatenated as high order bits, are sent to PC. Data read on Read Data1 port of Registers is sent to PC. Table 2. 2-bit control lines and their actions ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ (c) CMOV Rd, Rt, Rs In this instruction IR[31-26] = opcode, IR[25-21] = Rs, IR[20-16] = Rt and IR[15-11] = Rd. This is a "conditional move" instruction. The contents of register Rt are moved to register Rd if register Rs is not equal to zero. That is, if [Rs] != 0 then Rd <- [Rt]. ( [R] means contents of register R ). Clk 1 2 3 4 5 6 7 8 Clk 1 2 3 4 5 6 7 8 Clk 1 2 3 4 5 6 7 8 ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ (b) JALR Rs In this instruction IR[31-26] = opcode and IR[25-21] = Rs. This is a "Jump and link through register" instruction. PC+4 gets written into register 31 and then execution continues at the instruction whose address is given by the contents of register Rs. ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¢ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡ ¢ ¢¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ (a) LW Rt, offset(Rs) In this instruction, IR[31-26] = opcode, IR[25-21] = Rs, IR[20-16] = Rt and IR[15-0] = offset. This instruction loads into register Rt the contents of the memory location whose address is computed by adding the 16-bit signed offset to the base register (Rs). Name:____SOLUTION___ To reduce the number of signals you have to write assume that initially, at cycle 1, all signals are 0. Note that ALU sets Zero to 1 when the result of the ALU operation is zero. Also, note that since the instructions are word aligned, the 2 least significant bits of "Jump Address" are always zero. So bits 25 to 0 of the IR register are mapped to bits 27 to 2 of "Jump Address". You are asked to write the control sequence (i.e., the relevant control lines and their values) to fetch from memory and execute the following instructions: Control Signals IorD=0, MemRd=1 IRWrite=1, ALUSelA=0, ALUSelB=1, ALUOp=0, PCSource=1, PCWrite=1 MemRd=0, PCWrite=0, IRWrite=0, ALUSelA=0, ALUSelB=3, ALUOp=0, TargetWrite=1 AluSelA=1, AluSelB=0; ALUOp=2 WriteDataSel=2, RegDest=2, RegWRite=1, ZeroEnCond=1 RegWrite=0 Control Signals IorD=0, MemRd=1 IRWrite=1, ALUSelA=0, ALUSelB=1, ALUOp=0, PCSource=1, PCWrite=1 MemRd=0, PCWrite=0, IRWrite=0, ALUSelA=0, ALUSelB=3, ALUOp=0, TargetWrite=1 RegDest=1, WritedataSel=3, Regwrite=1, ZeroEnCond=0 RegWrite=0, PCSource=3, PCwrite=1 PCWrite=0 Control Signals IorD=0, MemRd=1 IRWrite=1, ALUSelA=0, ALUSelB=1, ALUOp=0, PCSource=1, PCWrite=1 MemRd=0, PCWrite=0, IRWrite=0, ALUSelA=0, ALUSelB=3, ALUOp=0, TargetWrite=1 TargetWrite=0, ALUSelA=1, ALUSelB=3, ALUOp=0, IorD=1, MemRd=1 WritedatSel=0, RegDest=0, RegWrite=1, ZeroEnCond=0 MemRd=0, RegWrite=0 Page 9 of 10 Targetwrite [31-28] 0 1 Target [31-0] [25-0] PCwrite 3 PCSource ZeroEnCond AluSelA 32 2 Name:____SOLUTION___ Shift left by 2 IorD MemRd MemWr AND IRWrite RegDest RegWrite N A N D 0 1 PC 0 Read Address [20-16] Instruction [25-0] 0 [25-21] WriteEnable Read reg 1 Read reg 2 Read Data1 Zero 1 Memory Memdata Write Address Registers 0 1 ALU 31 1 2 Write Data [15-0] Instr. Register [15-11] Write Reg Read Data 2 Write Data 4 2 3 Aluop 0 1 2 Whenever you assert a signal during a cycle be sure to deassert during the next cycle if this is necessary. The number of cycles required by each instruction type may be different. You can use as many cycles as you need but not more than 8 for each of the instructions. Figure 1. The Datapath with its control signals AluSelB 3 Sign Ext. WritedataSel [5-0] ALU control Page 10 of 10 ...
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This note was uploaded on 03/29/2008 for the course ECE 552 taught by Professor Wood during the Spring '05 term at University of Wisconsin.

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