Hazard conditions in Forwarding: EX-hazard (RAW) If (EX/MEM.RegWrite and (EX/MEM.Rd != 0) and (EX/MEM.Rd = ID/EX.Rs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.Rd !=0 and (EX/MEM/Rd = ID/EX.Rt)) ForwardB = 10 MEM-hazard (WAW) If (MEM/WB.RegWrite And (MEM/WB.Rd !=0) And (EX/MEM.Rd != ID/EX.Rs) And (MEM/WB.Rd = ID/EX.Rs)) ForwardA = 01 If (MEM/WB.RegWrite And (MEM/WB.Rd !=0) And (EX/MEM.Rd != ID/EX.Rt) And (MEM/WB.Rd = EX/MEM.Rt) ForwardB = 01 Load-Use Hazard If (ID/EX.MemRead And (ID/EX.rt = IF/ID.rs) OR (ID/EX.rt = IF/ID.rt))) Stall IF and ID by disabling PC and IF/ID register (if no forwarding, stall 2 cycles) Branch Hazards-Assume branch not taken, if mispredicted, flush the whole pipe-Assume branch taken “ “ Optimization: Move decision into second stage (need comparator (XOR and then OR == equal) and Adder) needs additional forwarding and hazard detection units penalty only one cycle versus 3 cycles still problem if branch is on result that is still in the pipe Branch prediction buffer aka branch history table: Small memory indexed by lower 10 bits of PC. Simple scheme: 1-bit Better: 2 bits: changed when prediction was wrong twice Pipelines • Exploit parallelism among the instructions in a sequential instruction stream. • Tme between instr (pipelined) = Time between instr (non-pipelined) / # of pipe stages • Speedup (assuming ideal cond.) = # of pipe stages • speedup reality < # of pipe stages • Pipelines increase instr. Throughput important metric of performance
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Central processing unit, CPU cache, miss rate, miss penalty, TLB MISS PAGE