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Unformatted text preview: Name:_____________________________________ Page 1 of 8 CS/ECE 552 Introduction to Computer Architecture Midterm Exam Monday, March 18, 1991 7:15-9:15 p.m Name:_________________________________________________________________________ Limit your answers to the space provided. Unnecessarily long answers will be penalized. If you use more space than is provided, you are probably doing something wrong. Use the back of each page for any scratch work. Write your last name on each page. Problem 1. Problem 2. Problem 3. Problem 4. Problem 5. Problem 6. Total ______________ (out of 15 points) ______________ (out of 25 points) ______________ (out of 15 points) ______________ (out of 14 points) ______________ (out of 14 points) ______________ (out of 18 points) ______________ (out of 101 points) Name:_____________________________________ Page 2 of 8 (1) Micro-operation Control Sequences (15 points) Part of the data path organization of a CPU is shown in the figure below. In this organization, the control points are at the inputs and outputs of all registers. There are eight registers, R0 through R7 in the register file. The contents of any one of the registers in the register file can be placed on the A bus. Likewise, any one of the registers can be loaded from the B bus. The interconnection paths to and from the other registers are indicated by the arrows. A Bus X
Register IR PC Status File MDR ALU Memory B Bus
MAR Write a sequence of control microoperations to fetch from memory and execute the following twoword instruction: BP -(R1), R2, addr where BP compares the two operands and branches to the address (addr) specified in the second word if the first operand is greater than the second operand. Therefore, the above instruction uses the autodecrement mode on register R1 to obtain the first operand and the register mode on register R2 to obtain the second operand for comparison. Assume that the following hold: (i) (ii) All addresses are word addresses, i.e., incrementing the contents of the PC, for example, by 1 will cause it to point to the next word in memory. The output of a register does not change until the end of the clock cycle in which it is loaded, i.e., you cannot output the new contents of the register in the same cycle that you latch data into the register. The ALU is capable of performing (among other things) the following operations in one clock cycle: INCX DECX SUBAX PASSA (iv) Add 1 to the contents of the X register Subtract 1 from the contents of the X register Subtract the value on the A bus from the X register Pass the contents of the A bus to the B bus (iii) The condition codes from an ALU operation get loaded into the Status register when a LoadStatus control point is asserted along with an ALU operation. The status registers contain Zero (Z), Sign (N), Carry (C), and Overflow (V) flags. Name:_____________________________________ For your convenience, part of the first step of the fetch phase is given below: Time Step 1 PCout, PASSA, MARin 2 4 6 8 10 12 14 13 11 9 7 5 3 Control Micro-operations Page 3 of 8 Comments (a) Name:_____________________________________ (2) Write the logic equations for the following signals, in the space provided: (20 points) Let Xi , Yi , Ci and Si , with i = 0, 1, ..., 63, represent the individual bits of the two operands, the carries, and the sums, respectively. Let G I and P I , i = 0,....,63 represent the first level i i generates and propagates. Let G II and P II , j = 0,...,15 represent the second level generates and proj j pagates, and let G III and P III , k = 0,..,3 represent the third level generates and propagates. k k GI = 0 G III = 0 P III = 0 C4 = C 16 = S0 = C 64 = P II = 0 PI = 0 G II = 0 The figure below shows a 64-bit carry lookahead adder with three levels of lookahead. Some signals are shown in the figure to give you an idea of the structure of the adder; however not all relevant signals are shown (for example the carries from the first level lookahead to the single-bit adders). Adder Design (25 points) 16-bit CLA 16-bit CLA 16-bit CLA Third Level Lookahead Second Level Lookahead G III 0 Single Bit Adders P III 0 Page 4 of 8 G II P II 0 0
First level Lookahead GI PI 0 0 C0 Name:_____________________________________ Page 5 of 8 (b) (5 points) What is the worst-case delay through this adder? Assume that each gate delay is time units, and all gates are available with up to 5 inputs. Show your calculations and reasoning. (3) (i) Short Questions (15 points) (3 points) What is pipelining? How does it improve the throughput of a job? (ii) (4 points) Give two reasons why the IBM 370 instruction set is more amenable to high-performance implementations than the VAX-11 instruction set. (iii) (8 points) You are to design a barrel shifter, to shift 8-bit numbers. Your barrel shifter must be able to shift an input number left by B bit positions, where 0 B 7. You have an unlimited number of 2-1 single-bit multiplexors and other logic elements available. Show the design of your barrel shifter. Name:_____________________________________ Page 6 of 8 (4) (i) Short Calculations (14 points) (6 points) A computer system consists of a CPU connected to a memory via a single bus as shown below. All programs and data reside in the memory. The bandwidth of the bus connecting the CPU and the memory is 5107 bits per second, and the memory can supply information at a peak rate of 108 bits per second. All instructions are 16 bits and, on the average, 24 bits of data need to be transferred between the CPU and memory to fetch the operands (and store the results) of an instruction. What is the maximum possible instruction execution rate of the computer system? Explain your answer in one short sentence. CPU Bus Memory (ii) Consider a hypothetical computer that uses 16 bit instructions. An address field (or operand specifier) for the instruction consists of 6 bits. The instruction set contains 2-address, 1-address and 0-address instructions. The computer must have 120 1-address instructions. (4 points) What is the maximum number of opcodes available for 2-address instructions? Show your work. (4 points) Given that the number of opcodes used for 2-address instructions is the maximum possible number (from your above calculation) and that the number of opcodes used for 1-address instructions is 120, what is the maximum number of available opcodes for 0-address instructions? Show your work. Name:_____________________________________ Page 7 of 8 (5) (i) Short Microprogramming Questions (14 points) (2 points) Two key limitations of microprogrammed control over hardwired control are: (ii) (2 points) Two key limitations of hardwired control over microprogrammed control are: (iii) (3 points) List three techniques that could be used to reduce the number of bits in a microprogrammed control store. (iv) (3 points) List three techniques that could be used to improve the performance of microprogrammed control. (v) (4 points) The microprogram control store of a certain computer is 1000 words 80 bits. The 80 bits in each word include a next address field. If the control store contains only 160 distinct microinstructions (excluding the next address field), how many total bits would be required to implement this control using nanoprogramming, and what is the percentage reduction in the number of bits in the control store with nanoprogramming? Show your work. Name:_____________________________________ Page 8 of 8 (6) True and False Questions (18 points) For each of the following statements, answer TRUE(T) if the statement is true and FALSE(F) if the statement is false. You will be credited 2 points for each correct answer and penalized 1 point for each incorrect answer. It is possible that you may perceive a question to be ambiguous. If that happens, please state any assumptions that you make in your answer. The minimum score for this question will be zero.
(i) It is impossible to distinguish between instructions and data in the memory of a stored program, von Neumann computer. (ii) Fan-in and fan-out limitations are of no concern in CPU design. (iii) In the PDP-11, the absolute addressing mode can be realized by using the autoincrement addressing mode with the PC. (iv) Efficient multi-way branching in microcode is accomplished by using a sequence of 2-way branch instructions. (v) A horizontal microprogram will have more steps that an equivalent vertical microprogram. (vi) In the IBM 370, the size of an instruction can vary from 1 to 61 bytes. (vii) In the HP 3000, a 16-bit instruction can sometimes contain 2 opcodes. (viii) The HP 3000 contains no user-addressable registers because the designers of the HP 3000 considered the speed of access to operands to be unimportant (ix) To sequence through a microprogram, a microprogram address register (PAR) is preferred over a microprogram program counter (PC), to distinguish it from the program counter (PC) used to sequence through the machine language program. ...
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This test prep was uploaded on 03/29/2008 for the course ECE 552 taught by Professor Wood during the Spring '05 term at Wisconsin.
- Spring '05
- Computer Architecture