Unformatted text preview: Name:_____________________________________ Page 1 of 9 CS/ECE 552 Introduction to Computer Architecture Midterm Exam Thursday, March 18, 1993 7:15-9:15 p.m Name:_________________________________________________________________________ Limit your answers to the space provided. Unnecessarily long answers will be penalized. If you use more space than is provided, you are probably doing something wrong. Use the back of each page for any scratch work. Problem 1. Problem 2. Problem 3. Problem 4. Problem 5. Problem 6. Total ______________ (out of 27 points) ______________ (out of 10 points) ______________ (out of 14 points) ______________ (out of 13 points) ______________ (out of 14 points) ______________ (out of 22 points) ______________ (out of 100 points) Name:_____________________________________ Page 2 of 9 (1) (i) Short Questions (27 points) Consider two machines, machines A and B, executing a program, PROG. Machines A and B execute 1.4107 and 1.2107 instructions, respectively, at a rate of 0.8 and 0.7 instructions per clock cycle, respectively. The clock cycle times of machines A and B are 30 and 35 nanoseconds, respectively. (a) Which machine is faster for executing PROG? Justify your answer by calculating the time taken by each machine to execute PROG. (5 points) (b) By how much. Show your work. (2 points) (ii) What is a load/store architecture? (4 points) (iii) What is a SET operation in the MIPS architecture. Give an example of its use. (4 points) (iv) What is the primary (implementation) disadvantage of variable size instructions? Explain your answer. (4 points) Name:_____________________________________ Page 3 of 9 (v) What is the primary (implementation) advantage of fixed size opcodes? Explain your answer. (4 points) (vi) What do we mean by a stored program computer? (4 points) (2) True and False Questions (10 points) For each of the following statements, answer TRUE(T) if the statement is true and FALSE(F) if the statement is false. You will be credited 2 points for each correct answer and penalized 1 point for each incorrect answer. It is possible that you may perceive a question to be ambiguous. If that happens, please state any assumptions that you make in your answer. The minimum score for this question will be zero. (i) More powerful instructions lead to higher performance since the total number of instructions executed is smaller for a given task with more powerful instructions. Pipelining improves performance by decreasing the latency of each instruction. A barrel shifter to carry out arbitrary shifts on a 64-bit number has 6 stages of multiplexors. The MIPS R2000 architecture has no explicit condition codes. Since an add operation has 3 operands (2 input and 1 output), add instructions must be 3-address instructions. (ii) (iii) (iv) (v) Name:_____________________________________ Page 4 of 9 (3) (i) Short questions (14 points) List one point in favor of, and one point against: (a) Microprogrammed Control over Hardwired Control (3 points) (b) Supporting an autoincrement addressing mode for accessing operands (3 points) (ii) What is a Program Address Register (PAR)? How is it different from a Program Counter (PC)? (4 points) (iii) What is system balance? How does the notion of system balance influence the design of a computer system? (4 points) Name:_____________________________________ Page 5 of 9 (4) Lookahead Incrementer (13 points) In this question, you are to design an 8-bit, one-level carry-lookahead incrementer, which adds a constant 1 to the contents of an 8-bit Program Counter. The incrementer does not have to perform any other functions. Assume that the maximum number of inputs of any gate if 5. (i) Show the design of your incrementer. You design should describe the functionality of each unit (using logic equations), and show how the units are connected. Excessive hardware in the design will be penalized. (10 points) Highlight the critical path through the incrementer. What is the delay through your incremeter? (3 points) (ii) Name:_____________________________________ (5) Microinstruction Fill in the table below with your microprogram. The fields of the microinstruction are: (i) y 1 , y 2 , y 3 , and y 4 are the bits representing the outputs of the control circuit, (ii) Next_Addr is the 2-bit address of the next microinstruction, (iii) Next_Addr_Mod is a 2-bit field indicating how the 2-bit address specified in the Next_Addr field is modified. Next_Addr_Mod = 00 means that the Next_Addr field is not modified, Next_Addr_Mod = 01 means that the input x is bit-ORed with bit 0 of the Next_Addr field; bit 1 is not modified; Next_Addr_Mod = 10 means that the input x is bit-ORed with bit 1 of the Next_Addr field; bit 0 is not modified; Next_Addr_Mod = 11 is undefined. The microinstruction format you are to use is: The finite-state machine describing the control circuit is shown in the figure below. Microprogrammed Control (14 points) In this problem, you are to use microprogrammed control to implement a finite-state machine (FSM) for a control circuit, in manner similar to how the control FSM is implemented in the book. The control circuit has a 1-bit input x, and four 1-bit outputs, y 1 , y 2 , y 3 , and y 4 . yi = 1 if the machine is in state si, and 0 otherwise. 1-bit y1 y1 x, input SIGNALS CONTROL y2 1-bit y2 y3 y4 1-bit y3 x=0 x=0 x=1 1-bit y4 s1 s4 Microinstruction Address 11 10 01 00 y1 y2 y3 Next_Addr_Mod y4 2-bits x=1 x=0 x=1 Next_Addr_Mod
s2 s3 Next_Addr x=0 x=1 3-bits Next_Addr Page 6 of 9 Name:_____________________________________ Page 7 of 9 (6) Control Operations and Sequencing (22 points) Consider the datapath shown in figure 1. The datapath is same as the one in the H&P Textbook for multicycle implementation. The actions corresponding to the values of the control signals are as follows: IorD TargetWrite None Table 1. 1-bit control lines and their actions Signal ALUSeIB Value 0 1 Table 2. 2-bit control lines and their actions Please note that since the instructions are always word aligned, the bits 1 and 0 of Jump address are always 0 and 0. So the bits 25-0 from the instruction form the bits 27-2 in the Jump Address. 2 PCSource ALUOp 0 1 2 0 1 2 Action Second ALU input from the register given by rt field Second ALU input from the contant 4 Second ALU input from the sign extended lower 16 bits of IR ALU does an add ALU does a subtract Func field determines the ALU operation ALU output sent to the PC for writing Target register contents sent to the PC for writing The PC[31-28] concatenated with IR[25-0] and 00 (for PC[1-0]) is sent to the PC for writing PCWriteCond None PCWrite None IRWrite RegWrite MemtoReg RegDst Signal MemRd MemWr ALUSeIA Action if deasserted None None The First ALU operand is the PC The register destination number for register write comes from the rt field None The value fed to the register write data is from the ALU The PC supplies the address to the memory None Action if asserted Memdata <- Memory[Read Address] Memory[Write Address] <- Write Data First ALU operand comes from the register given by rs field The register destination number for the register write comes from the rd field Register[Write Register] <- Write data The value fed to the register write data is from the memory ALU output suplies the address to the memory The value from memory is written into the Instruction register The PC is written; the source is controlled by the PCSource The PC is written if the Zero output of ALU is active The ALU ouput is written into the register Target Name:_____________________________________ (c) STORE_INC Rsrc2, Immed(Rsrc1) In this instruction, IR[31-26] = opcode, IR[25-21] = Rsrc2, IR[20-16] = Rsrc1, IR[15-0] = Immed . The opcode is "store in memory and increment index", and the meaning of the instruction is to store the value in the Register Rsrc2 at the location given by the address = contents of Rsrc1 + Immed. Immed is an immediate operand. Then increment the Register Rsrc1 by 4. (b) JR Rsrc In this instruction, IR[31-26] = opcode, IR[25-21] = Rsrc. The opcode is "Jump thru register", and the meaning of the instruction is to jump to the address in the register Rsrc, i.e., the CPU would start fetching instructions from the address that is in the register Rsrc. (a) SLT Rdest, Rsrc2, Rsrc1 In this instruction, IR[31-26] = opcode, IR[25-21] = Rsrc2, IR[20-16] = Rsrc1, IR[15-11] = Rdest, IR[5-0] = ALU opcode to compare the inputs and give a 1 or a 0 at the output , depending on whether input2 of ALU > input1 of ALU or not, respectively. The opcode is "set less than", and the meaning of the instruction is to set the register Rdest to 1 if Rsrc2 is less than Rsrc1, otherwise set Rdest to 0. Write the sequence of control (i.e., the relevant control lines and their values) to fetch from memory and execute the following instructions: Assume that you have a variable number of clocks to execute each of the instructions (i.e., if you need more than a fixed number of clocks to execute any of these instructions, you may use as many as you need, but not more than 8 clocks). Clk 1 2 3 4 5 6 7 8 Clk 1 2 3 4 5 6 7 8 Control Signals MemRd = 1, IRWrite = 1, IorD = 0, Control Signals Page 8 of 9 Clk 1 2 3 4 5 6 7 8 Control Signals Name:_____________________________________ Page 9 of 9 PCSource PCWriteCond PC[31-0] Zero Zero IRWrite AND PCWrite MemData[31-26] OR Opcode |IorD MemRd MemWr PC[31-0] RegDst RegWrite ALUSeIA Jump Address 1 2 Instruction[25-0] = JumpAddress[27-2] PC[31-28] = JumpAddress[31-28] JumpAddress[1-0] = 00 0 M u x MemData[25-21] rs Read Register1 Read 0 Zero M u Read Daat1 M u x Write Register Registers ALU Target 1 x MemData[20-16] rt 0 1 M u PC x Address Memory Write Address Write Data 1 MemData[10-6] shamt 0 0 Read MemData[15-11] rd 1 Register2 M u Write Read Data2 0 M 1 u x x Data 4
2 MemData[5-0] func Instruction Register Sign Control ext ALU ALUSeIB ALUop TargetWrite Figure 1. The DataPath with the Control signals MemtoReg ...
View Full Document
- Spring '05
- Computer Architecture, Central processing unit, operand