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Unformatted text preview: Name:_____________________________________ Page 1 of 9 CS/ECE 552 Introduction to Computer Architecture Midterm Exam Thursday, October 24, 1991 7:15-9:15 p.m Name:_________________________________________________________________________ Limit your answers to the space provided. Unnecessarily long answers will be penalized. If you use more space than is provided, you are probably doing something wrong. Use the back of each page for any scratch work. Write your last name on each page. Problem 1. Problem 2. Problem 3. Problem 4. Problem 5. Problem 6. Problem 7. Total ______________ (out of 18 points) ______________ (out of 18 points) ______________ (out of 8 points) ______________ (out of 10 points) ______________ (out of 10 points) ______________ (out of 17 points) ______________ (out of 20 points) ______________ (out of 101 points) Name:_____________________________________ Page 2 of 9 (1) Micro-operation Control Sequences (18 points) Consider the data path of a CPU as shown below. PC IR MDR MAR BUS B ACC R0 BUS A RN -1 A ALU
STATUS The ONLY valid register transfers, and other operations are shown in the table below. Furthermore, one and only one transfer/operation may be carried out in a given clock cycle. (Note that there is no direct path between bus A and bus B; such transfers must go through the ALU). Operation/Transfer Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Operation/Transfer Semantics PC [PC] + 1; done through the ALU PC [A] ACC [A] + [ACC] IR [A] ACC [A] + [Ri ] ACC [A] Ri [A] A [MDR] A [ACC] A [Ri ] A [PC] MDR [A]; Write Memory Start Read Memory Start MAR [PC] MAR [ACC] MAR [Ri ] Wait for Memory Function Complete (WMFC) Clear A END Name:_____________________________________ Page 3 of 9 (i) Write a sequence of control microoperations to fetch from memory and execute the following two-word instruction: Word 1 Word 2 The opcode is ADD, and the semantics (meaning) of the instruction are as follows: Add the contents of the memory word whose address is obtained by adding the "Displacement" specified in word 2, to the contents of register R j , to the contents of the word that is indirectly addressed by Rk (i.e., Rk contains the effective address of the second operand as well as the result). The machine is word addressable, and only one word is fetched at a time. To assist you in your answer, the first few transfers/operations are given below. (12 points) 14, 1, 13, 17, 8, 4, (ii) For the data path, indicate in which steps the following gates will be opened. For example, the steps in which the gate MARIN is opened are: MARIN : 14, 15, 16 (a) ACCOUT : (b) ALUOUT : (this is the gate that connects the ALU to bus B) Opcode R j and mode Rk and mode Displacement (2 points) (4 points) (a) Name:_____________________________________ (2) (Hint: Many of the equations are simpler than the equivalent equations for an adder) Write the logic equations for the following signals, in the space provided: (14 points) Let Xi , Ci and Si , with i = 0, 1, ..., 63, represent the individual bits of the operand X, the carries, and the sums, respectively. Let G I and P I , i = 0,....,63 represent the first level generates and propagates. Let i i G II and P II , j = 0,...,15 represent the second level generates and propagates, and let G III and P III , k = 0,..,3 j j k k represent the third level generates and propagates. C 64 = C8 = P II = 0 G II = 0 PI = 0 GI = 0 S4 = The figure below shows a 64-bit INCREMENTER with three levels of carry lookahead. The purpose of the incrementer is to add a constant 1 to a number X, i.e., carry out the operation X+1. Some signals are shown in the figure to give you an idea of the structure of the incrementer; however not all relevant signals are shown (for example the carries from the first level lookahead to the single-bit incrementers). Incrementer Design (18 points) 16-bit CLI 16-bit CLI 16-bit CLI Third Level Lookahead Second Level Lookahead G III 0 Single Bit Incrementers P III 0 Page 4 of 9 G II P II 0 0
First level Lookahead GI PI 0 0 C0 Name:_____________________________________ Page 5 of 9 (b) (4 points) What is the worst-case delay through this incrementer? Assume that each gate delay is time units, and all gates are available with up to 5 inputs. Show your calculations and reasoning. (3) (8 points) Consider the following Boolean, F, function of 4 variables, A, B, C, and D. F = C.D + A.B +A.B.D + A.B.C (i) Give a set of inputs that cause a static hazard if the function is realized as above. (4 points) (ii) Give a realization of the above function that is free of static hazards. (4 points) Name:_____________________________________ Page 6 of 9 (4) (10 points) Consider the computer system shown in the figure below.
BUS CPU MEMORY I/O DEVICE The bandwidths of the devices are: Device Bus Memory I/O Device Bandwidth (bytes/sec) 1107 1107 8104 The CPU needs an average of 10 bits from memory, and 0.1 bits from the I/O device, to execute an instruction. (i) What is the peak instruction execution rate of the CPU? Assume that all CPU functions can be carried out as fast as possible. Show your work. (6 points). (ii) Define the utilization of a resource to be the bandwidth of the resource used divided by the bandwidth available. When the CPU is executing at its peak execution rate, as calculated in part i), what is the utilization of the bus, the memory, and the I/O device? Fill in your answers in the table below. (4 points) Device Utilization Bus Memory I/O Device Name:_____________________________________ Page 7 of 9 (5) (10 points) Consider a horizontal microprogram that has 4K words of 90 bits each. It has been decided that you want to minimize the total amount of control memory used to store the microprogram for the machine. You have three options to the base choice (the base choice is the horizontal microprogram with 4K words of 90 bits each). The choices are: Option A Use vertical microprogramming. Doing so would decrease the width of each microinstruction to 60 bits, but would result in 30% more microinstructions. Option B Use a next address field with the horizontal microprogram. In the horizontal microprogram, 25% of all the microinstructions are microbranch instructions. Option C Use a next address field with option A (Option A was a vertical microprogram that would result the number of bits in each microinstruction to 60, but would result in 30% more microinstructions). 25% of the microinstructions are microbranch instructions. Which option would you choose, and why? For credit, your answer MUST be supported with a detailed calculation of the bit requirements for each option. Name:_____________________________________ Page 8 of 9 (6) (i) (17 points) Short Questions How does pipelining speed up the execution of a program? How is the throughput of a pipeline related to the latency of execution of tasks in the pipeline? (5 points) (ii) (a) Assume that we make an enhancement to a computer so that some mode of execution is improved by a factor of 5. Under what circumstances will the overall speedup that is obtained be 3? (Speedup is defined as the execution time in the old machine divided by the execution time in the new machine.) (3 points) (b) If the enhanced mode is used 50% of the time, but measured as a percentage of the total execution time when the enhanced mode is used, what is the overall speedup? What percentage of the original execution time is converted to the faster mode? (3 points) (iii) Consider a computer with a 16-bit instruction format very similar to the PDP-11, as shown below: 4 F1 3 F2 3 F3 3 F4 3 F5 Ten out of the sixteen codes in the field F1 are used to specify 2-address instructions (with fields F2 and F3 specifying the register and addressing mode for the first address, and F4 and F5 specifying the register and addressing mode for the second address). One code in field F1 is used to specify 1-address instructions. What is the maximum number of opcodes available for 1-1/2 address instructions (for 1-1/2 address instructions, field F3 is the 1/2 address register, and fields F4 and F5 are used to specify the full address)? How many opcodes are available for 1-address instructions? Show your work. (6 points) Name:_____________________________________ Page 9 of 9 (7) True and False Questions (20 points) For each of the following statements, answer TRUE(T) if the statement is true and FALSE(F) if the statement is false. You will be credited 2 points for each correct answer and penalized 1 point for each incorrect answer. It is possible that you may perceive a question to be ambiguous. If that happens, please state any assumptions that you make in your answer. The minimum score for this question will be zero. (i) Pipelining improves performance by decreasing the latency of execution of each instruction. (ii) A barrel shifter to shift a 32-bit input number left, by up to 31 bit positions, has 8 stages of two-to-one (2-1) multiplexors. (iii) Microprogrammed control is generally faster than hardwired control. (iv) In a load/store architecture, the instruction set contains computation instructions that operate on memory operands. (v) Program sequencing using a program counter is a special case of program sequencing with a program address register. (vi) One of the main reasons to have general-purpose registers in the CPU is to reduce the demand for the CPUto-memory bandwidth. (vii) A zero address instruction has no operands specified explicitly. (viii) Consider two computers A and B, running a program P. It is impossible for computer A to have a lower execution time that computer B, for program P, if computer A actually executes more instruction than computer B for program P. (ix) In a von Neumann computer, it is possible to tell whether a bit string stored in memory is an instruction or a data item simply by looking at the address. (x) In the MIPS R2000, there are 4 flags for condition codes, namely, N, V, Z, and C. ...
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This test prep was uploaded on 03/29/2008 for the course ECE 552 taught by Professor Wood during the Spring '05 term at Wisconsin.
- Spring '05
- Computer Architecture