final.sp92_sol - [1(i memory-mapped I/O(ii program...

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[1] (i) memory-mapped I/O (ii) program controlled I/O (iii) DMA controller (iv) pretranslation (did not cover in class) (v) daisy chain (vi) banking or interleaving (vii) janmming or von Neumann rounding (viii) array multiplier (ix) Booth's recoding (x) spatial and temporal locality [2] (i) I/O devices can be accessed with ordinary memory-accessing instructions (ii) trap is synchronous whereas interrupt is asynchronous (did not cover in class; covered in CS/ECE 354) (iii) DMA controller. If CPU is given priority it could hog the bus and/or perturb a high-speed transfer that is being carried out by the DMA. (did not cover in class) (iv) 2**8 x 8 = 4K bits per chip. 4K x 64 = 32Kbytes total. (v) 29 is (0 2 -1 1) and -12 is (0 -1 1 0) (vi) (a) number of pins is minimized, (b) easier to implement error correction (e.g., a SECDED scheme) when chip is used to build bigger memory systems. [3] Assume that leading digit for a normalized number is to the right of the fractional point. (This is the case with FP number systems that use bases other than 2 but is not
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final.sp92_sol - [1(i memory-mapped I/O(ii program...

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