Unformatted text preview: Name:_____________________________________ Page 1 of 9 CS/ECE 552 Introduction to Computer Architecture Midterm Exam Thursday, March 17, 1994 5:05-7:05 p.m Name:_________________________________________________________________________ Limit your answers to the space provided. Unnecessarily long answers will be penalized. If you use more space than is provided, you are probably doing something wrong. Use the back of each page for any scratch work. Write your last name on each page. Problem 1. Problem 2. Problem 3. Problem 4. Problem 5. Problem 6. Total ______________ (out of 24 points) ______________ (out of 8 points) ______________ (out of 8 points) ______________ (out of 20 points) ______________ (out of 11 points) ______________ (out of 24 points) ______________ (out of 95 points) Write the logic equations for the following signals, in the space provided. (The equations should be in terms of the inputs to the logic block for which they represent the outputs.) GI = 1 PI = 1 G III = 1 P III = 1 C8 = C 32 = S3 = (a) Name:_____________________________________ (1) (12 points) Let Xi , Yi , Ci and Si , with i = 0, 1, ..., 63, represent the individual bits of the two operands, the carries, and the sums, respectively. Let G I and P I , i = 0,....,63 represent the first level generates and propagates. i i Let G II and P II , j = 0,...,15 represent the second level generates and propagates, and let G III and P III , k = 0,..,3 j j k k represent the third level generates and propagates. S 16 = The figure below shows a 64-bit carry lookahead adder with three levels of lookahead. Some signals are shown in the figure to give you an idea of the structure of the adder; however not all relevant signals are shown (for example the carries from the first level lookahead to the single-bit adders). Adder Design (24 points) 16-bit CLA 16-bit CLA 16-bit CLA Third Level Lookahead Second Level Lookahead G III 0 Single Bit Adders P III 0 Page 2 of 9 G II P II 0 0
First level Lookahead GI PI 0 0 C0 Signal C 32 S 16 S3 Time Ready Comments (c) (b) Name:_____________________________________ (2) Calculate the number of gates of each type in the lookahead logic (include all levels and do not count gates in the 64 single-bit adders). Show your work. (6 points) (6 points) Assume that each gate delay is time units, and all gates are available with up to 5 inputs. Further assume that all Xi , all Yi , and C 0 are ready at time 0. In the table below, show at what time the chosen signal value is ready. Use the comment column for any comments (comments will be used to determine partial credit in case of an incorrect answer). (6 points) Barrel Shifter (8 points) You are to design a barrel shifter, to rotate 8-bit numbers. Your barrel shifter must be able to rotate an input number left by B bit positions, where 0 B 7. You have an unlimited number of 2-1 single-bit multiplexors and other logic elements available. Show the design of your barrel shifter. Page 3 of 9 Name:_____________________________________ Page 4 of 9 (3) Machine Performance (8 points) Consider two different implementations M1 and M2, of the same instruction set. There are four classes of instructions (A, B, C, and D) in the instruction set. M1 has a clock rate of 50 MHz and M2 has a clock rate of 75 MHz. The fraction of all instructions that belong to a particular class, and the average number of cycles for each instruction in the two implementations are as below: Class A B C D Percentage of instructions in class 20% 20% 30% 30% CPI on M1 1 2 3 4 CPI on M2 2 2 4 4 Which implementation of the instruction set is faster, and by how much? Show your work. Name:_____________________________________ Page 5 of 9 (4) (i) Pipelined Implementations (20 points) What are data hazards in a pipeline? (3 points) (ii) How can bubbles due to data hazards in a pipeline be reduced (or even eliminated)? (3 points) (iii) How do we introduce bubbles in a pipeline when we need to? That is, how do we keep an instruction in a given stage in the pipeline, without preventing instructions that entered the pipeline earlier from progressing in the pipeline? (3 points) (iv) What are branch hazards in a pipeline? (3 points) (v) Suggest two solutions (and explain what they are) to reduce the number of bubbles caused by branch hazards in a pipeline. (4 points) (vi) In a typical pipelined computer the pipelined datapath has separate memory elements for instructions and data. Why is this so? (4 points) Name:_____________________________________ Page 6 of 9 (5) (i) Short Questions (11 points) Give 2 reasons why peak MFLOPS is not a good metric for comparing different machines. (4 points) (ii) Suppose you have already designed a CPU and implemented the control to execute a particular instruction set. Now, you want to add another instruction to the instruction set, and want your CPU to execute the new instruction. Would your task be easier if the control was implemented using hardwired or microprogrammed control? Why? (3 points) (iii) What are zero-address instructions? (2 points) (iv) Where are the operands of a zero-address instruction? (2 points) Name:_____________________________________ Page 7 of 9 (6) Datapath (24 points) Consider the datapath shown in figure 1. It is almost the same as the one in the H&P textbook for the multicycle implementation. The only difference is that there is the option to specify register 31 as the target register during write to the registers. The actions corresponding to the values of the control signals are as follows (IR is used in place of "Instruction Register"): Signal MemRd MemWr ALUSelA Action if deasserted (0) None None PC is the first ALU operand RegWrite MemtoReg IorD None The value fed to the registers as write data comes from the ALU PC supplies the address to memory None None None None IRWrite PCWrite PCWriteCond TargetWrite Action if asserted (1) Memdata <- Memory[Read Address] Memory[Write Address] <- Write Data The register whose number is given by bits [25-21] of the instruction register is the first ALU operand Register[Write Register] <- Write data The value fed to the registers as write data comes from memory ALU's output is the address supplied to memory The value from memory (MemData) is written into the Instruction register (IR) PC is written; PCSource controls the input ALU's output gets written into the PC register if Zero is active ALU's output gets written into the Target register Table 1. 1-bit control lines and their actions Value 0 1 2 3 0 1 2 0 1 2 0 1 2 Signal ALUSeIB ALUOp PCSource RegDst Action Second ALU input is the register given by the bits [20-16] of IR Second ALU input is 4 Second ALU input is the lower 16 bits of IR sign-extended to 32 bits Second ALU input is the 16 lower bits of IR sign-extended to 32 bits and shifted left by 2 ALU does an add ALU does a subtract FUNC field of IR (bits [5-0]) specifies the ALU operation ALU's output is sent to PC Target register contents are sent to PC Bits [31-28] of the PC, bits [25-0] of the IR and 00 (2 bits) are concatenated in order (higher to lower) and fed as input to PC Bits [20-16] of IR specify which register is going to be written if RegWrite is active Register 31 gets written if RegWrite is active Bits [15-11] of IR specify which register is going to be written is RegWrite is active Table 2. 2-bit control lines and their actions Clk 1 2 3 4 5 6 7 8 Clk 1 2 3 4 5 6 7 8 Clk 1 2 3 4 5 6 7 8 Control Signals Control Signals Control Signals Name:_____________________________________ (c) AABZ Rs, Rt, Imm In this instruction IR[31-26] = opcode, IR[25-21] = Rs, IR[20-16] = Rt and IR[15-0] = Imm. This an "add and branch if zero" instruction. The contents of register Rs are added to the contents of register Rt, the result is then written to register Rt. In addition, if the result is zero, program execution resumes at the instruction whose address is calculated as follows: the 16-bit wide Imm field is sign-extented and then shifted left by 2 bits to form a 32-bit number which is then added to the current value of PC. (b) JALR Rs In this instruction IR[31-26] = opcode and IR[25-21] = Rs. This is a "Jump and link through register" instruction. PC+4 gets written into register 31 and then execution continues at the instruction whose address is given by the contents of register Rs. Assume that the FUNC field of this instruction specifies that the ALU should pass its first input directly to its output and that the two least significant bits are ignored on a write to PC. (a) SUB Rd, Rs, Rt In this instruction, IR[31-26] = opcode, IR[25-21] = Rs, IR[20-16] = Rt and IR[15-11] = Rd. The contents of register Rt are subtracted from those of Rs and the result is placed in register Rd. Note that since the instructions are word aligned, the 2 least significant bits of "Jump Address" are always zero. So bits 25 to 0 of the IR register are mapped to bits 27 to 2 of "Jump Address". You are asked to write the control sequence (i.e., the relevant control lines and their values) to fetch from memory and execute the following instructions: Page 8 of 9 Name:_____________________________________ Page 9 of 9 To reduce the number of signals you have to write assume that initially, at cycle 1, all signals are 0. Whenever you assert a signal during a cycle be sure to deassert during the next cycle if this is necessary. The number of cycles required by each instruction type may be different. You can use as many cycles as you need but not more than 8 for each of the instructions. PCWrite PCWriteCond TargetWrite
0 1 2 Target [31-28] [31-0] [25-0] Jump Address 32 PCSource AluSelA IorD MemRd MemWr
0 1 IRWrite RegDst RegWrite [31-0] 0 Shift left by 2 PC Read address Memory Write MemData address Write Data Instruction [25-0] Instruction Register [25-21] [20-16]
0 Read reg1 Read reg2
1 2 1 Zero ALU Read Data 1 AluSelB
0 Registers Write Reg Write Data Read Data 2 4 [15-11] 31 1 2 3 0 AluOp
1 [15-0] MemtoReg 16 Sign 32 Ext. Shift left by 2 ALU Control Figure 1. The Datapath with its control signals Name:_____________________________________ Page 10 of 9 ...
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This test prep was uploaded on 03/29/2008 for the course ECE 552 taught by Professor Wood during the Spring '05 term at University of Wisconsin.
- Spring '05
- Computer Architecture