MC9S08GB60_Data_Sheet.pdf

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Unformatted text preview: MC9S08GB60 MC9S08GB32 MC9S08GT60 MC9S08GT32 MC9S08GT16 Data Sheet HCS08 Microcontrollers MC9S08GB60/D Rev. 2.3 12/2004 freescale.com MC9S08GB/GT Data Sheet Covers: MC9S08GB60 MC9S08GB32 MC9S08GT60 MC9S08GT32 MC9S08GT16 MC9S08GB60 Rev. 2.3 12/2004 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1.0 4/25/2003 Description of Changes Initial release 1.1 Electricals change, appendix A only 1.2 Electricals change, appendix A only 1.3 10/2/2003 Added module version table; clarifications 1.4 10/29/2003 Fixed typos and made corrections and clarifications 1.5 11/12/2003 Added 1-MHz IDD values to Electricals, appendix A 2 2/10/2004 Changed format of register names to enable reuse of code (from SCIBD to SCI1BD, even when only one instance of a module on a chip) Added new device: MC9S08GT16 to book. Added new 48-pin QFN package to book. BKGDPE description in Section 5 — changed PTD0 to PTG0. Changed typo in CPU section that listed MOV instruction as being 6 cycles instead of 5 (Table 8-2). 2.2 9/2/2004 Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5; updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1; updated ICG electricals Table A-9 and added a figure 12/01/2004 Minor changes to Table 7-4, Table 7-5, Table A-9; Clarifications in Section 11.10.6, “SCI x Control Register 3 (SCIxC3)”, Section 11.7, “Interrupts and Status Flags”, Section 11.8.1, “8- and 9-Bit Data Modes”, PTG availability in 48-pin package (see Table 2-2) 2.3 This product incorporates SuperFlash® technology licensed from SST. Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2004. All rights reserved. MC9S08GB/GT Data Sheet, Rev. 2.3 4 Freescale Semiconductor List of Chapters Chapter 1 Introduction.............................................................................. 17 Chapter 2 Pins and Connections ............................................................. 23 Chapter 3 Modes of Operation ................................................................. 33 Chapter 4 Memory ..................................................................................... 39 Chapter 5 Resets, Interrupts, and System Configuration ..................... 61 Chapter 6 Parallel Input/Output ............................................................... 77 Chapter 7 Internal Clock Generator (ICG) Module ................................. 97 Chapter 8 Central Processor Unit (CPU)............................................... 125 Chapter 9 Keyboard Interrupt (KBI) Module ......................................... 145 Chapter 10 Timer/PWM (TPM) Module..................................................... 151 Chapter 11 Serial Communications Interface (SCI) Module.................. 167 Chapter 12 Serial Peripheral Interface (SPI) Module.............................. 187 Chapter 13 Inter-Integrated Circuit (IIC) Module .................................... 203 Chapter 14 Analog-to-Digital Converter (ATD) Module ......................... 219 Chapter 15 Development Support ........................................................... 235 Appendix A Electrical Characteristics...................................................... 259 Appendix B Ordering Information and Mechanical Drawings................ 281 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor 5 Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 1.4 Overview .........................................................................................................................................17 Features ...........................................................................................................................................17 1.2.1 Standard Features of the HCS08 Family .........................................................................17 1.2.2 Features of MC9S08GB/GT Series of MCUs .................................................................17 1.2.3 Devices in the MC9S08GB/GT Series ............................................................................18 MCU Block Diagrams .....................................................................................................................19 System Clock Distribution ..............................................................................................................21 Chapter 2 Pins and Connections 2.1 2.2 2.3 Introduction .....................................................................................................................................23 Device Pin Assignment ...................................................................................................................23 Recommended System Connections ...............................................................................................26 2.3.1 Power ...............................................................................................................................28 2.3.2 Oscillator ..........................................................................................................................28 2.3.3 Reset ................................................................................................................................28 2.3.4 Background / Mode Select (PTG0/BKGD/MS) ..............................................................29 2.3.5 General-Purpose I/O and Peripheral Ports .......................................................................29 2.3.6 Signal Properties Summary .............................................................................................31 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................33 Features ...........................................................................................................................................33 Run Mode ........................................................................................................................................33 Active Background Mode ................................................................................................................33 Wait Mode .......................................................................................................................................34 Stop Modes ......................................................................................................................................34 3.6.1 Stop1 Mode ......................................................................................................................35 3.6.2 Stop2 Mode ......................................................................................................................35 3.6.3 Stop3 Mode ......................................................................................................................36 3.6.4 Active BDM Enabled in Stop Mode ................................................................................36 3.6.5 LVD Enabled in Stop Mode .............................................................................................37 3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................37 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor 7 Section Number Title Page Chapter 4 Memory 4.1 4.2 4.3 4.4 4.5 4.6 MC9S08GB/GT Memory Map .......................................................................................................39 4.1.1 Reset and Interrupt Vector Assignments ..........................................................................39 Register Addresses and Bit Assignments ........................................................................................41 RAM ................................................................................................................................................46 FLASH ............................................................................................................................................46 4.4.1 Features ............................................................................................................................47 4.4.2 Program and Erase Times ................................................................................................47 4.4.3 Program and Erase Command Execution ........................................................................48 4.4.4 Burst Program Execution .................................................................................................49 4.4.5 Access Errors ...................................................................................................................50 4.4.6 FLASH Block Protection .................................................................................................51 4.4.7 Vector Redirection ...........................................................................................................52 Security ............................................................................................................................................52 FLASH Registers and Control Bits .................................................................................................53 4.6.1 FLASH Clock Divider Register (FCDIV) .......................................................................54 4.6.2 FLASH Options Register (FOPT and NVOPT) ..............................................................55 4.6.3 FLASH Configuration Register (FCNFG) .......................................................................56 4.6.4 FLASH Protection Register (FPROT and NVPROT) ......................................................56 4.6.5 FLASH Status Register (FSTAT) .....................................................................................58 4.6.6 FLASH Command Register (FCMD) ..............................................................................59 Chapter 5 Resets, Interrupts, and System Configuration 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Introduction .....................................................................................................................................61 Features ...........................................................................................................................................61 MCU Reset ......................................................................................................................................61 Computer Operating Properly (COP) Watchdog .............................................................................62 Interrupts .........................................................................................................................................62 5.5.1 Interrupt Stack Frame ......................................................................................................63 5.5.2 External Interrupt Request (IRQ) Pin ..............................................................................64 5.5.2.1 Pin Configuration Options ..............................................................................64 5.5.2.2 Edge and Level Sensitivity ..............................................................................65 5.5.3 Interrupt Vectors, Sources, and Local Masks ..................................................................65 Low-Voltage Detect (LVD) System ................................................................................................67 5.6.1 Power-On Reset Operation ..............................................................................................67 5.6.2 LVD Reset Operation .......................................................................................................67 5.6.3 LVD Interrupt Operation .................................................................................................67 5.6.4 Low-Voltage Warning (LVW) ..........................................................................................67 Real-Time Interrupt (RTI) ...............................................................................................................67 MC9S08GB/GT Data Sheet, Rev. 2.3 8 Freescale Semiconductor Section Number 5.8 Title Page Reset, Interrupt, and System Control Registers and Control Bits ...................................................68 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................68 5.8.2 System Reset Status Register (SRS) ................................................................................69 5.8.3 System Background Debug Force Reset Register (SBDFR) ...........................................71 5.8.4 System Options Register (SOPT) ....................................................................................71 5.8.5 System Device Identification Register (SDIDH, SDIDL) ...............................................72 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) ...............................73 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ..........................74 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ..........................75 Chapter 6 Parallel Input/Output 6.1 6.2 6.3 6.4 6.5 6.6 Introduction .....................................................................................................................................77 Features ...........................................................................................................................................79 Pin Descriptions ..............................................................................................................................79 6.3.1 Port A and Keyboard Interrupts .......................................................................................79 6.3.2 Port B and Analog to Digital Converter Inputs ...............................................................80 6.3.3 Port C and SCI2, IIC, and High-Current Drivers ............................................................80 6.3.4 Port D, TPM1 and TPM2 .................................................................................................81 6.3.5 Port E, SCI1, and SPI ......................................................................................................81 6.3.6 Port F and High-Current Drivers .....................................................................................82 6.3.7 Port G, BKGD/MS, and Oscillator ..................................................................................82 Parallel I/O Controls ........................................................................................................................82 6.4.1 Data Direction Control ....................................................................................................83 6.4.2 Internal Pullup Control ....................................................................................................83 6.4.3 Slew Rate Control ............................................................................................................83 Stop Modes ......................................................................................................................................84 Parallel I/O Registers and Control Bits ...........................................................................................84 6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) ................................................84 6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) ...............................................86 6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) ...............................................87 6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ..............................................89 6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ................................................90 6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) ..................................................92 6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ..............................................93 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor 9 Section Number Title Page Chapter 7 Internal Clock Generator (ICG) Module 7.1 7.2 7.3 7.4 7.5 Introduction .....................................................................................................................................99 7.1.1 Features ..........................................................................................................................100 7.1.2 Modes of Operation .......................................................................................................101 External Signal Description ..........................................................................................................101 7.2.1 Overview ........................................................................................................................101 7.2.2 Detailed Signal Descriptions .........................................................................................102 7.2.2.1 EXTAL— External Reference Clock / Oscillator Input ...............................102 7.2.2.2 XTAL— Oscillator Output ...........................................................................102 7.2.3 External Clock Connections ..........................................................................................102 7.2.4 External Crystal/Resonator Connections .......................................................................102 Functional Description ..................................................................................................................103 7.3.1 Off Mode (Off) ..............................................................................................................103 7.3.1.1 BDM Active .................................................................................................103 7.3.1.2 OSCSTEN Bit Set .........................................................................................103 7.3.1.3 Stop/Off Mode Recovery ..............................................................................104 7.3.2 Self-Clocked Mode (SCM) ............................................................................................104 7.3.3 FLL Engaged, Internal Clock (FEI) Mode ....................................................................105 7.3.3.1 FLL Engaged Internal Unlocked ..................................................................105 7.3.3.2 FLL Engaged Internal Locked ......................................................................106 7.3.4 FLL Bypassed, External Clock (FBE) Mode ................................................................106 7.3.5 FLL Engaged, External Clock (FEE) Mode ..................................................................106 7.3.5.1 FLL Engaged External Unlocked .................................................................106 7.3.5.2 FLL Engaged External Locked .....................................................................107 7.3.6 FLL Lock and Loss-of-Lock Detection .........................................................................107 7.3.7 FLL Loss-of-Clock Detection ........................................................................................107 7.3.8 Clock Mode Requirements ............................................................................................108 7.3.9 Fixed Frequency Clock .................................
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  • Summer '16
  • Scott, Richards
  • Central processing unit, Processor register, Freescale Semiconductor

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