Digital Design Verification with SystemVerilog - 6 - VMM.pdf - SystemVerilog[Verification Verification Methodology Manual Advanced Hardware Design

Digital Design Verification with SystemVerilog - 6 -...

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Verification Methodology Manual Topics 1 [email protected] Advanced Hardware Design & Verification SystemVerilog [Verification] VMM was developed by Synopsys© as a framework for verifying designs using SystemVerilog http:// T here are a large number of VMM resources on the web (which I have shamelessly stolen from for this lecture). http:// M essage Service vmm_log S imulation Control vmm_env D ata and Transactions vmm_data T ransactors vmm_xactor E xtensible Verification Component xvc_xactor I nterfacing and Transactors vmm_channel VMM
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Verification Methodology Manual Overview The Layered T estbench Approach 2 [email protected] Advanced Hardware Design & Verification SystemVerilog [Verification] D river Monitor D esign U nder T est A ssertions S ignal C ommand S ignal C ommand T ransactor F unctional F unctional S coreboard C hecker G enerators T ests
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Verification Methodology Manual Verification Environment Test Harness 3 [email protected] Advanced Hardware Design & Verification SystemVerilog [Verification] module tb ; // 1. Variables declarations: These are variables local // to the testbench logic clk = 1 ’b 0, reset_n ; // 2. Interface instantiations: These are the DUT // interfaces to provide the connection between the // stimulus drivers/monitors and the DUT. fifo_if #(. setup_time ( 3 ), . hold_time(3)) f_if (.*); // 3. Program instantiations: The program provides the // control for testing the DUT. A testbench may // contain more than one program. fifo_test_pgm utest_pgm (. fifo_if_0 ( f_if ), . reset_n ( reset_n )); // 4. DUT instantiations: This the device under test. fifo fifo_rtl_1 (. f_if(f_if ), .*); // 5. Binding of property modules to DUT instances: // Property module typically includes assertions // and coverage requirements. // 6. Clock generators: These generators emulate the // clocks in the system. initial forever # CLK_HPERIOD clk = ~ clk ; endmodule : ex_top D esign U nder T est T ests E nvironment
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Verification Methodology Manual Verification Environment interface (Synchronous FIFO) 4 [email protected] Advanced Hardware Design & Verification SystemVerilog [Verification] interface fifo_if (input wire clk , input wire reset_n ); timeunit 1 ns; timeprecision 100 ps; logic write , read ; wire full , empty ; word_t rdata , wdata ; parameter hold_time = 3, setup_time = 5 ; clocking mon_cb @(posedge clk ); // FIFO Monitor if. default input # setup_time output # hold_time ; input empty, full, data_out, error , data_in, push, pop ; endclocking : mon_cb modport fifo_mon_if_mp (clocking mon_cb ); clocking driver_cb @(posedge clk ); default input # setup_time output # hold_time ; input empty , full , data_out , error ; output data_in, push, pop ; endclocking : driver_cb modport fdrvr_if_mp (clocking driver_c b ); endinterface Virtual interface Virtual interface D esign U nder T est
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Verification Methodology Manual Verification Environment vmm_env 5 [email protected] Advanced Hardware Design & Verification SystemVerilog [Verification] class Environment extends vmm_env; virtual fifo_if vir_if; /************************************************ * Write Side of FIFO * ************************************************/ // Channel instance fifo_xactn_channel fifo_push_channel, // Generator instance
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