100%(1)1 out of 1 people found this document helpful
This preview shows page 1 - 5 out of 43 pages.
Object Oriented Verification•Abstraction in HDL’s•Alook at previous attempts•Classes•Objects•Example•UML•Inheritance/Reuse•Constructors (Continued)•Packages[email protected]u.edu1Advanced Hardware Design & VerificationSystemVerilog
[email protected][Verification] Object Oriented VerificationOO Programming BasicsLet’s go over some of the terminology that we will be using as we proceed into the realm of OOP.Class– a basic building block containing routines and variables. The analogue in Verilog is a module. (Real-World example would be a Blue-Print of a house)Object– an instance of a class. In Verilog, you need to instantiate a module to use it. (Real-World example would be the actual house)Handle– a pointer to an object. In Verilog, you use the name of an instance when you refer to signals and methods from outside the module. An OOP handle is like the address of the object, but is stored in a pointer that can only refer to one type. (Real-World example would be an address to the house)Property – A variable that holds data. In Verilog, this is a signal such as a registeror wire. (Real-World example would be an doors in the house)2Method– the procedural code that manipulates variables, contained in tasksand functions. Verilog modules have tasks and functions plus initial and always blocks. (Real-World example would be a opening or closing the doors)Material for this slide has been “heavily borrowed” from Aldec’s lecturesAdvanced Hardware Design & VerificationSystemVerilog
[Verification] Object Oriented VerificationAbstraction in HDLsAlgorithmTLMRTLNew, large digital systems require at leastTransactionLevel Modeling, which is requiresamoreabstractandcomplexstructurewhich is best represented using OP.GATEClassicalHardwareDescription Languages(HDLs) – VHDL and Verilog areoperating at the procedural level to let you design at RTL or behavioral level.The cost of working at a very highlevel of abstraction is that we loosethe ability to control the minutedetails of the implementation.Abstract models are gradually refined downto the RTL/gate level where we can controlall of the knobs and switches of the design.[email protected]3Material for this slide has been “heavily borrowed” from Aldec’s lecturesAdvanced Hardware Design & VerificationSystemVerilog
[Verification] Object Oriented VerificationIn my day… we didn’t have OOP[email protected]4How we used to do things…Classical languages (BASIC, C, Verilog, VHDL) abstract control and data separatelySubroutines (procedures/tasks and functions) describe what the program can doData types (arrays, records/structures) define data that can be manipulated by subroutinesIn large designs that extensively use language resources, this separation of control and data can lead to confusion…Can I useto_integerfunction withSTD_LOGIC_VECTOR argument?