Digital Design Verification with SystemVerilog - 2 - Basic Object Oriented Verification {v03_27_2014 - Advanced Hardware Design Verification

Digital Design Verification with SystemVerilog - 2 - Basic Object Oriented Verification {v03_27_2014

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Object Oriented Verification A bstraction in HDL’s A look at previous attempts C lasses O bjects E xample UML I nheritance/Reuse C onstructors (Continued) P ackages [email protected]u.edu 1 Advanced Hardware Design & Verification SystemVerilog
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[email protected] [Verification] Object Oriented Verification OO Programming Basics L et’s go over some of the terminology that we will be using as we proceed into the realm of OOP. Class – a basic building block containing routines and variables. The analogue in Verilog is a module. (Real-World example would be a Blue-Print of a house) Object – an instance of a class. In Verilog, you need to instantiate a module to use it. (Real- World example would be the actual house) Handle – a pointer to an object. In Verilog, you use the name of an instance when you refer to signals and methods from outside the module. An OOP handle is like the address of the object, but is stored in a pointer that can only refer to one type. (Real-World example would be an address to the house) Property – A variable that holds data. In Verilog, this is a signal such as a register or wire. (Real-World example would be an doors in the house) 2 Method – the procedural code that manipulates variables, contained in tasks and functions. Verilog modules have tasks and functions plus initial and always blocks. (Real- World example would be a opening or closing the doors) Material for this slide has been “heavily borrowed” from Aldec’s lectures Advanced Hardware Design & Verification SystemVerilog
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[Verification] Object Oriented Verification Abstraction in HDLs Algorithm TLM RTL N ew, large digital systems require at least Transaction Level Modeling , which is requires a more abstract and complex structure which is best represented using OP. GATE C lassical Hardware Description Languages (HDLs) – VHDL and Verilog are operating at the procedural level to let you design at RTL or behavioral level. T he cost of working at a very high level of abstraction is that we loose the ability to control the minute details of the implementation. A bstract models are gradually refined down to the RTL/gate level where we can control all of the knobs and switches of the design. [email protected] 3 Material for this slide has been “heavily borrowed” from Aldec’s lectures Advanced Hardware Design & Verification SystemVerilog
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[Verification] Object Oriented Verification In my day… we didn’t have OOP [email protected] 4 H ow we used to do things… Classical languages (BASIC, C, Verilog, VHDL) abstract control and data separately S ubroutines (procedures/tasks and functions) describe what the program can do D ata types (arrays, records/structures) define data that can be manipulated by subroutines I n large designs that extensively use language resources, this separation of control and data can lead to confusion… C an I use to_integer function with STD_LOGIC_VECTOR argument?
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