Digital Design Verification with SystemVerilog - 2 - Connecting the Testbench and the Design {v05_19 - SystemVerilog Digital Design

Digital Design Verification with SystemVerilog - 2 - Connecting the Testbench and the Design {v05_19

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Unformatted text preview: SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Assertions • Types of Assertions • Immediate Assertions • Syntax • Actions • Messages • Concurrency Assertions • Sequences • Sequences within Sequences • Implication Operators • Properties • Putting it all together [email protected] 1 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions What is an Assertion An assertion is a statement that a certain property must be true. Assertion checking is a form of white box verification. It requires knowledge of internal structures of the design. The main purpose of assertion checkers is to improve observability. There are many types of assertions: • • immediate • Assertions test for a condition at the current time. concurrent • Assertions test for a sequence of events spread over multiple clock cycles. • The evaluation is associated with a clock edge [email protected] 2 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Overview An immediate assertion, like an if statement, simply checks that, at the time it is executed, the condition evaluates to TRUE. This simple zero-time test is not sufficient for supporting assertions in hardware designs. concurrent assertions describe behavior that spans over time. You should avoid using waveform viewing to check a response. It should be reserved for debugging. Instead of looking for specific signal relationships in a waveform viewer, specify these same relationships using assertions. The assertions will be continuously and reliably checked, for the entire duration of the simulation, for all simulations. They will provide a specification of the intended functionality of the design. Should your design be picked up by another designer, your original intent will be communicated along with your original code [Writing Testbenches using SystemVerilog by Janick Bergeron] Why are assertions used in design? We use it in design to automatically verify whether or not the code is not following the protocol definition. Note: Synthesis tools are smart enough to recognize assertions and ignore them. [email protected] 3 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Syntax An immediate assertion is test of an expression the moment the statement is executed. [name :] assert (expression) [pass_statement] [else fail_statement] The assert statement can be used in place an “if” statement. It clearly indicates that you are using this code for Verification instead of design. Checking functionality using an if statement bus.cb.request <= 1; repeat (2) @bus.cb; if (bus.cb.grant != 1’b1) $display("Error, grant != 1"); // rest of the test Checking functionality using an assertion bus.cb.request <= 1; repeat (2) @bus.cb; a1: assert (bus.cb.grant == 1’b1); else $error(“grant !=1”); CLK REQUEST [email protected] GRANT 4 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Actions and Messages An immediate assertion can have a message or action that occurs when the assertion is met, or fails to be met. These statements are completely optional and typically only used to communicate error conditions. . . . . a1 : assert (bus.cb.grant == 1’b1) $display(“The bus has responded with a grant”); Pass Condition else $display(“The bus has failed to respond with a grant”); Fail Condition . . . . CLK REQUEST GRANT [email protected] 5 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions The Simulation Scheduler Post-Poned Original Verilog Scheduler Active Pre-Poned Pre-Active Simulation of design code in modules. Inactive New scheduler states, and or redefined states, for SystemVerilog NonBlocking Note: If the input to assertion is from clocking block skew must be specified using #1step, otherwise an error will be generated. IEEE Std 1800-2005 [email protected] Values for assertion sampled here. Meaning, this is the only value the assertion cares about. Sampling design signals for testbench input Inactive NonBlocking Observed Re-Active Post-Poned The assertion is evaluated here. Execution of testbench code in programs Pre-Poned 6 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Concurrency Defined Concurrent assertions describe behavior that spans over time. They are specified using the clock tick as a basis for determining cycles. In other words, expressions in assertions are always tied to a clock value. interface arb_if(input bit clk); logic [1:0] grant, request; logic rst; Concurrent assertions are clock based, i.e. the inputs to the assertion are only sampled during a clock edge. property request_2state; @(posedge clk) disable iff (rst) $isunknown (request) == 0; else $display(“error: unknown value of signal”); endproperty The SVLRM defines a clock tick as an atomic moment that spans no duration of time. assert_request_2state : assert property (request_2state); endinterface Note: The keyword property distinguishes a concurrent assertion from an immediate assertion. Simulation Clock Ticks Clock Ticks 1 2 3 4 5 6 7 8 9 10 11 request [email protected] 7 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Ingredients Concurrent assertions describe behavior that spans over time. They are specified using the clock tick as a basis for determining cycles. In other words, expressions in assertions are always tied to a clock value. assert property (@posedge clk) req |-> gnt ##1 (done && !err)); Verification Directives assert, cover, assume, expect Property Declaration A property can be named or unnamed Sequential Regular Expressions A sequence can be named or unnamed Used to build Used to build Used to build Boolean Expressions [email protected] Verilog, SystemVerilog and special assertion methods that return true/false results. Note: This diagram has been taken directly from a lecture from Sutherland HDL 8 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Boolean Expressions Boolean Expressions can only evaluate to either TRUE or FALSE. TRUE = 1 FALSE = 0, X, or Z There are two types of Boolean expressions occur in concurrent assertion properties: 1) iff (if-and-only-if) can be used in conjunction with the disable keyword to preempt the evaluation of an assertion. 2) And, the sequences that make up a property in a concurrent assertion. Note: concurrent assertions are clock based, i.e. the inputs to the assertion are only sampled during a clock edge. [email protected] Variable types that cannot be used in Boolean Expressions: - shortreal, real, realtime - string - event - chandle - class - dynamic and associative arrays 9 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Sequences within Sequences We can embed sequences in other sequences to create more complex rules. sequence <sequence_identifier> [ ( tf_port_list ) ]; sequence_expr; Syntax endsequence [ : <sequence_identifier> ] sequence s; a ##1 b ##1 c; endsequence The sequence “s” is referenced inline in this sequence . sequence rule; Example @(posedge sysclk) trans ##1 start_trans ##1 s ##1 end_trans; endsequence The above two sequences get translated into the following: sequence rule; @(posedge sysclk) trans ##1 start_trans ##1 a ##1 b ##1 c ##1 endsequence [email protected] end_trans ; Example 10 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Sequence Blocks – Delay Operators A sequence is a series of Boolean expressions (evaluate to True/False) occur in concurrent assertion properties: ## - represents a “cycle delay” This specifies that req shall be true on the current clock tick, and gnt shall be true on the second subsequent clock tick req ##2 gnt Example ##n - specifies a fixed delay of n clock cycles The following specifies that signal b shall be true on the Nth clock tick after signal a: a ##N b // check b on the Nth sample Example ##[min_count:max_count] - specifies a range of clock cycles In cases where the delay can be any value in a range, a time window can be specified as follows: [email protected] req ##[4:32] gnt Example 11 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Sequences - Linear Linear Sequences – finite list of expressions in linear order of increasing time. sequence <sequence_identifier> [ ( tf_port_list ) ]; sequence_expr; endsequence [ : <sequence_identifier> ] Syntax Example sequence req ##1 gnt ##1 ~req; endsequence A sequence can be declared in any of the following: — module — interface — program — clocking block — package — compilation-unit scope [email protected] 1st Expression 2nd Expression 3rd Expression CLK REQ GNT 12 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Sequences - Implication Operators A property is an implication if it has either of the forms shown below: “non-overlapped” implication operation ”overlapped” implication operation sequence_expr |-> property_expr Syntax If the condition is true, sequence evaluation starts immediately • If the condition is false, the sequence acts as if it succeeded • property p_req_ack; @(posedge clk) mem_en |-> (req ##2 ack); endproperty : p_req_ack Example sequence_expr |=> property_expr If the condition is true, sequence evaluation starts at the next clock. 13sequence acts as • If the13 condition is false, the if it succeeded • property p_req_ack; @(posedge clk) mem_en |=> (req ##2 ack); endproperty : p_req_ack clk clk mem_en mem_en req req ack ack [email protected] Syntax Example 13 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Sequence - Value Change Functions $sampled (expression [, clocking_event]) Syntax $rose ( expression [, clocking_event]) $fell ( expression [, clocking_event]) $sampled returns the sampled value of the expression with respect to the last occurrence of the clocking event $rose returns true if the LSB of the Syntax expression changed to 1. Otherwise, it returns false. $fell returns true if the LSB of the Syntax expression changed to 0. Otherwise, it returns false. $stable returns true if the value of $stable ( expression [, clocking_event]) Syntax the expression did not change. Otherwise, it returns false $past ( expression1 [, number_of_ticks] [, expression2] [, clocking_event]) $past returns the sampled value of the expression that was present number_of_ticks prior to the time of evaluation of $past. [email protected] Syntax 14 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Property Blocks A property defines a behavior of the design. A property can be used for verification as an assumption, a checker, or a coverage specification. In order to use the behavior for verification, an assert, assume, or cover statement must be used. A property declaration by itself does not produce any result. property <name_of_property> (<inputs_to_property>) [sequence | expressions | implications] Syntax endproperty [ : <name_of_property> ] property my_prop (q, d) @(posedge clk) (q == $past(d)) endproperty : my_prop assert property (my_prop (d, q)); [email protected] Sample signal for continuous assertion. Actual Assertion A property can be declared in any of the following: — module — interface — program — clocking block — package — compilation-unit scope Example 15 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Examples property LED_valid_transtions (@(posedge clk) disable iff (~reset_b) (state == IDLE |=> // .. Followed by.. (state == LED0 ##5000 state == LED1 ##5000 state == LED2 ##5000 Example state == LED3 ##5000 state == LED4 ##5000 state == LED5 ##5000 state == LED6 ##5000 state == LED7))); endproperty : LED_valid_transtions assert property (LED_valid_transitions) else $error(“Illegal state transition to LED sate\n”); What does this assertion do? (In Class Quiz) [email protected] property no_two_ads; Example @(posedge busclk) disable iff (rst) (ADSOut |=> !ADSOut); endproperty 16 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions disable iff [email protected](posedge clk or negedge reset_n) if (reset_n) sm_check_for_onehot : assert ($onehot (state)) else $fatal(0, "Fatal Error: More than one bit asserted in SM: 0x%08x", state); [email protected](posedge clk or negedge reset_n) sm_check_for_one_hot: assert disable iff (reset_n) ($onehot(state)) else $fatal(0, "Fatal Error: More than one bit asserted in SM: 0x%08x", state); [email protected] 17 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Synthesis An assertion has another benefit that in-line checkers (if-statements) do not. // synthesis translate_off if (xyz) begin @(posedge clk); if (xyz) $error(“Error: Should’ve been de-asserted”); end In order to ensure that our checker // synthesis translate_on code does not get synthesized, we need to add compiler pragmas. property deassert_test @(posedge clk); xyz |=> ~xyz; endproperty : deassert_test assert property (deassert_test); [email protected] Assertions do not require any pragmas to turn them off for synthesis purposes. 18 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Severity Levels SystemVerilog defines assertion failure-reporting (or info-reporting) system tasks Reports run-time fatal message $fatal [ ( finish_number, “message”, message_arguments ) ; finish_number is 0, 1, or 2 and controls the level of information generated by the tool upon termination. Default: $error[ ( “message”, message_arguments ) ; Terminates simulation with an error code Reports run-time error message Does not terminate simulation $warning[ ( “message”, message_arguments ) $info[ ( “message”, message_arguments ) [email protected] ; ; Suppressible runtime warning General information, nothing actually happens. 19 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions System Functions Assertions are commonly used to evaluate certain specific characteristics of a design implementation, such as whether a particular signal is “one-hot”. The following system functions are included to facilitate such common assertion functionality: returns true if only one bit in the expression is 1 $onehot (<expr>) returns true if at most 1 bit of the expression is 1. $onehot0 (<expr> ) True if any bit in the expression is X or Z (^expression === 1’bx) $isunknown (<expr>) The return type of these assertions is bit 1 = true ; 0 = false $countones (<expression>) [email protected] Note: Another useful function provided for the boolean expression is $countones, to count the number of ones in a bit vector expression. An X or Z value of a bit is not counted towards the number of ones. 20 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design Immediate/Concurrent assertions Putting it all together module led_fsm ( /**************************************************************************** clk, // I * In-Line Verification Code * reset_n, // I ****************************************************************************/ led); // O [07:00] [email protected](posedge clk or negedge reset_n) /**************************************************************************** if (reset_n) * Configuration and Parameters * *****************************************************************************/ sm_check_for_onehot : assert ($onehot (state)) else $fatal(0, "Fatal Error: More than one bit asserted in SM: 0x%08x", state); input clk; input reset_n; output [07:00] led; // One-Hot Style parameter IDLE = parameter LED0 = parameter LED2 = parameter LED4 = parameter LED6 = Parameter Encoding 9'b000000001; 9'b000000010; parameter 9'b000001000; parameter 9'b000100000; parameter 9'b010000000; parameter LED1 LED3 LED5 LED7 = = = = 9'b000000100; 9'b000010000; 9'b001000000; 9'b100000000; /****************************************************************************** * Combinational Logic * *****************************************************************************/ [email protected]* case(state) IDLE: next_state LED0: next_state LED1: next_state LED2: next_state LED3: next_state LED4: next_state LED5: next_state LED6: next_state LED7: next_state endcase = = = = = = = = = [email protected] time_has_passed time_has_passed time_has_passed time_has_passed time_has_passed time_has_passed time_has_passed time_has_passed time_has_passed ? ? ? ? ? ? ? ? ? LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED0 : : : : : : : : : IDLE; LED0; LED1; LED2; LED3; LED4; LED5; LED6; LED7; Note: This example can be found on Blackboard . 21 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design clocking Blocks • Communication between modules • interface • provides bundling of port signals • provide an abstract encapsulation of communication between blocks • modport interface extensions • examples • Functionality (routines, assertions) • clocking blocks • improving your test-bench • examples device1 interface device2 interface bus_a (input clock); logic [07:00] address; logic [31:00] data; bit valid; bit rd_wr; endinterface : bus_a [email protected] 22 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design clocking Blocks Verilog – Communicating between modules Wishbone Master DAT_O DAT_I WE_O SEL_O STB_O ACK_I CYC_O module top ( ); adr wdat rdat we sel stb ack cyc ADR_I DAT_I DAT_O WE_I SEL_I STB_I Wishbone Slave ADR_O ACK_O CYC_I This sort of connectivity is simple when only a handful of pins were involved. wire [31:0] adr, wdat, rdat; wire we, sel, stb, ack, cyc; wb_master i_master (.ADR_O(adr), .DAT_O(wdat), .DAT_I(rdat), .SEL_O(sel), .STB_O(stb), .ACK_I(ack), .CYC_O(cyc)); wb_slave i_slave (.ADR_I(adr), .DAT_I(wdat), .DAT_O(rdat), .SEL_I(sel), .STB_I(stb), .ACK_O(ack), .CYC_I(cyc)); [email protected] module wb_master ( (ADR_O, // O [31:00] DAT_O, // O [31:00] DAT_I, // I [31:00] WE_O, // O SEL_O, // O STB_O, // O ACK_I, // I CYC_O); // O . . . . . . . . endmodule module wb_slave ( (ADR_I, // I [31:00] DAT_I, // I [31:00] DAT_O, // O [31:00] WE_I, // I SEL_I, // I STB_I, // I ACK_O, // O CYC_I);// I . . . . . . . . endmodule 23 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design clocking Blocks interface • Provides a new hierarchical structure – Encapsulates interconnect and communication – Separates communication from functionality – Eliminates "wiring" errors – Enables abstraction in the RTL A simple interface is a bundle of wires Just like a simple struct is a bundle of variables int i; logic [7:0] a; int i; logic [7:0] a; interface intf; int i; logic [7:0] a; endinterface : intf typedef struct { int i; logic [7:0] a; } s_type; [email protected] 24 SystemVerilog Digital Design & Synthesis [Verification] Connecting the Testbench and the Design clocking Blocks interface With the increasing complexity of designs, you can end up designing modules whose so...
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