Digital Design Verification with Verilog - 0 - Verifying Designs with Verilog {v04_26_2014}.pdf - Digital Design Verification with Verilog CSE 320

Digital Design Verification with Verilog - 0 - Verifying Designs with Verilog {v04_26_2014}.pdf

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Author: Kyle Gilsdorf Contact Info: [email protected] Website: V erifying HDL Designs using Verilog H ow should we test? (Positive/Negative Testing) R andomized Testing C ode Coverage (Branch, Condition, Statement, Toggle) W hat is Functional Coverage H ierchical References F ileIO and StdIO U nit Level vs. Full-Chip Testing fork-join C locks & Reset Task B us Functional Models # delays and ` timescale functions T oday, we are going to talk about the following concepts: Verifying HDL Designs using Verilog Overview CSE 320: Digital Design and Synthesis Digital Design Verification with Verilog
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Bugs Found? Write Tests Analyze Results Simulate Tests Test Name Test Description good_test T he goal of this test is to verify that the LED’s do not stop the blinking pattern until the correct sequence of key presses has been entered. bad_test T he goal of this test is to verify that the LED’s continue to blink in their specified pattern even when an incorrect sequence has been entered. Create Test Plan T his is the most basic form of testing. Fix RTL? Fix Test? Tests Remai n Verifying HDL Designs using Verilog What kind of tests should I write? Are you good test or a bad test? CSE 320: Digital Design and Synthesis Digital Design Verification with Verilog
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I f we had an infinite about of time, we could write a test for every single possible input to achieve 100% Coverage . It is unlikely that we will have this amount of time on our hands. more on this later… T his is where one looks at the benefits offered by Random testing… T he challenge of random testing is building a test that is capable of predicting the output given any input. D irected Testing R andomized Testing W hat about INVALID inputs that could never occur in nature? Verifying HDL Designs using Verilog What kind of tests should I write? Random Input (kind of liking throwing darts) CSE 320: Digital Design and Synthesis Digital Design Verification with Verilog
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V erilog allows us to write rules to limit the range of possible inputs. INVALID INPUT INVALID INPUT VALID INPUT (this input can actually occur…) Simulation Time B utton Press Duration 0 Clocks 1 Clocks - 1 Clocks Clocks 0 ns ns module Button_Press_Tb ; parameter lower_duration = 100 ; parameter upper_duration = 200 ; integer delay ; initial begin delay = $random( ); if (( delay >= lower_duration ) & ( delay <= upper_duration )) $display (" Randomization successful : Var = %0d ", delay ); else $display(" Randomization failed "); end endmodule Verifying HDL Designs using Verilog What kind of tests should I write? How can we limit randomness (guard rails) CSE 320: Digital Design and Synthesis Digital Design Verification with Verilog Note : Be careful when constraining random inputs and you might make random input impossible to generate or limit your inputs more than intended.
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W e can run/write as many tests (random or directed) as we want, but unless we know what we have covered, it doesn’t really matter. Toggle Coverage: C ounts each time a logic node transitions from one state to another.
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