Digital Design with Verilog - 0 - Combinational Logic - 00 - Verilog-HDL Basics (HDL Design) {v04_26 - Digital Design with Verilog Combinational Logic

Digital Design with Verilog - 0 - Combinational Logic - 00 - Verilog-HDL Basics (HDL Design) {v04_26

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Combinational Logic Verilog - HDL Basics (HDL Design) Overview CSE 320: Digital Design and Synthesis Digital Design with Verilog Author: Kyle D. Gilsdorf Contact Info: [email protected] Website: D igital Design with Verilog C ombinational Logic V erilog-HDL Basics (HDL Design) B uilt-In Primitives U ser-Defined Primitives D ataflow Modeling B ehavioral Modeling S tructural Modeling
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• IEEE 1364-2005 Verilog Standard • IEEE 1364.1-2002 Verilog RTL Synthesis V erilog Synthesis Interoperability • IEEE Standard for SystemVerilog U nified Hardware Design, Specification, and Verification Language Combinational Logic Verilog - HDL Basics (HDL Design ) CSE 320: Digital Design and Synthesis Digital Design with Verilog
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Combinational Logic Verilog - HDL Basics (HDL Design ) CSE 320: Digital Design and Synthesis Digital Design with Verilog Behavior Physical Structural Processors, memories Registers, FUs, MUXs Gates, flip-flops Transistors Sequential programs Register transfers Logic equations/FSM Transfer functions Cell Layout Modules Chips Boards E ach axis represents type of description Behavioral D efines outputs as function of inputs A lgorithms but no implementation Structural I mplements behavior by connecting components with known behavior Physical G ives size/locations of components and wires on chip/board Examples: FSM gates, flip-flops (same level) FSM transistors (lower level) FSM X registers, FUs (higher level) FSM X processors, memories (higher level) FSM = finite state machine FU = functional unit S ynthesis converts behavior at given level to structure at same level or lower
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. 1 0 L ongest Path L ogic Cone P rimary Inputs P rimary Output Combinational Logic Verilog - HDL Basics (HDL Design) What is Combinational Logic? CSE 320: Digital Design and Synthesis Digital Design with Verilog
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module name ( ports ); Configuration Parameters Signals Assign Statements Combinational Logic Synchronous Logic Instances endmodule Configuration Parameters : Details the direction and names of the ports and global constants that are used within the design. Modules : A module is the basic building block of a Verilog Design. Signals : Wires and Registers are used to store and pass along values in the design. Assign Statements : Used to drive a value onto a net ( wire ). Note: The continuous assignment is used to assign values to nets. Combinational Logic : Made up of SEQUENTIAL statements inside of an always construct that repeats continuously throughout the duration of the simulation. Synchronous Logic : Made up of PARALLEL statements inside of an always construct that repeats continuously throughout the duration of the simulation.
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