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Combinational LogicVerilog-HDL Basics (HDL Design)OverviewCSE 320: Digital Design and SynthesisDigital Design with Verilog•Author:Kyle D. Gilsdorf•Contact Info:[email protected]•Website: •Digital Design with Verilog•Combinational Logic•Verilog-HDL Basics (HDL Design)•Built-In Primitives•User-Defined Primitives•Dataflow Modeling•Behavioral Modeling•Structural Modeling
• IEEE 1364-2005 Verilog Standard–• IEEE 1364.1-2002 Verilog RTL Synthesis–Verilog Synthesis Interoperability•• IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language•Combinational LogicVerilog-HDL Basics (HDL Design)CSE 320: Digital Design and SynthesisDigital Design with Verilog
Combinational LogicVerilog-HDL Basics (HDL Design)CSE 320: Digital Design and SynthesisDigital Design with VerilogBehaviorPhysicalStructuralProcessors, memoriesRegisters, FUs, MUXsGates, flip-flopsTransistorsSequential programsRegister transfersLogic equations/FSMTransfer functionsCell LayoutModulesChipsBoardsEach axis represents type of descriptionBehavioralDefines outputs as function of inputsAlgorithms but no implementationStructuralImplements behavior by connecting components with known behaviorPhysicalGives size/locations of components and wires on chip/boardExamples:FSM →gates, flip-flops (same level)FSM →transistors (lower level)FSM X registers, FUs (higher level)FSM X processors, memories (higher level)FSM = finite state machineFU = functional unitSynthesis converts behavior at given level to structure at same level or lower
.10Longest PathLogic ConePrimary InputsPrimary OutputCombinational LogicVerilog-HDL Basics (HDL Design)What is Combinational Logic?CSE 320: Digital Design and SynthesisDigital Design with Verilog
modulename(ports );Configuration ParametersSignalsAssign StatementsCombinational LogicSynchronous LogicInstancesendmoduleConfiguration Parameters: Details the direction and names of the ports and global constants that are used within the design.Modules: A module is the basic building block of a Verilog Design.Signals: Wires and Registers are used to store and pass along values in the design.Assign Statements: Used to drive a value onto a net (wire). Note:The continuous assignment is used to assign values to nets.Combinational Logic: Made up of SEQUENTIALstatements inside of an always construct that repeats continuously throughout the duration of the simulation.Synchronous Logic: Made up of PARALLELstatements inside of an always construct that repeats continuously throughout the duration of the simulation.