Lab4.pdf

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Introduction to Computer Architectures 1 ICAR Laboratory : EDSAC The aim of this lab is to illustrate how instructions and data can be represented within a computer. In addition to this we will also be looking at how a typical computer architecture implements its fetch – decode – execute cycle. To illustrate these ideas a software simulation of the Electronic Delay Storage Automatic Calculator (EDSAC) will be used. EDSAC was developed in 1949 and was one of first stored program computers based on the von Neumann computer architecture. Note , you must use Windows 10 for this lab. The original website which contains this application and additional information on this computing machine can be found at: However , for the purposes of this lab we shall be running the simulator locally. To start the EDSAC simulator select : Start -> All programs -> Hardware Development -> EDSAC -> EdsacPC This will launch the simulator as shown in figure 1. The GUI is divided into two sections, a toolbar containing all the main user options and the EDSAC simulator window, replicating the type of interface that would have been found on the original computer. The round black panel represents the main memory monitor i.e. a cathode ray oscilloscope, which was used to display data stored in the 32 long tube mercury delay lines. Each long tube (memory bank) can store 32, short integer (16bit) data values. A binary “one” is represented by a GREEN pixel and a “zero” by a dull pixel. Note , by default all main memory locations are reset to zero. Left click on the ‘Hints’ tick box within the toolbar window, then move the cursor over the data bits in a row . As you do so the address and possible data values of these memory locations will be displayed in the bottom panel of the toolbar window. Note , make sure you understand were each word boundary is within the display i.e. data words 0 – 31. To look at the data stored in different memory banks i.e. delay lines 1 – 31 click on the ‘Long Tank’ spin box located in the middle of the bottom panel. This allows you to scroll up and down through the main memory space 32 words at a time. The bottom left panel within the simulator windows displays the contents of the five short tanks or registers (black rectangles) : Order Tank : implements the computer’s instruction register, storing the current instruction fetched from main memory. Within an EDSAC program the term ‘Order’ was used instead of ‘Instruction’. Mike Freeman 08/11/2016
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Introduction to Computer Architectures 2 Sequence Control Register (SCR) : also known as the P registers, implements the computer’s program counter, displaying the address of the current instruction to be executed. Multiplier : operand register for the hardware multiplier unit Multiplicand : operand register for the hardware multiplier unit Accumulator : result register storing the output of addition, subtractions and multiplication instructions Figure 1 : toolbar (top), EDSAC simulator window (bottom) Each register is divided into a number of fields e.g. sign bit, long / short integer,
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  • Winter '19
  • oussama jadayel
  • Computer Architecture, Central processing unit, Processor register, Von Neumann architecture

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