Lab14.pdf

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Introduction to Computer Architectures 1 ICAR Software Laboratory : MIPS64 Lab 1 The aim of this lab is to introduce the MIPS64 processor, its instruction set syntax and simulator. This processor is very similar to the DLX processor discussed in the lectures (sometimes pronounced “deluxe”), as shown in figure 1. The main difference between these processors is the MIPS64 uses 64bit registers and data memory. Background , the DLX processor derived its name from the average of the numerical values of other RISC processors of its time e.g. AMD 29K, IBM801, RISC 1, MIPS 1000 etc, which gave a result of 560, or DLX in Roman numerals. Figure 1 : DLX processor architecture The MIPS64 processor uses a load-store (RISC) architecture i.e. most instructions access their operands from one or more of the 32 × 64bit general purpose registers. Note , two of these registers are assigned special roles. Register zero (R0) is hardwired with the value zero, data written to this ‘register’ will be lost, reading will return a zero value. Register 31 is reserved i.e. use by ‘special’ instructions, in general it should not be used by the programmer. In addition to the ‘32’ general purpose registers the processor also has a program counter and interrupt address registers. Format Bits 31 26 25 21 20 16 15 11 10 6 5 0 R-type 0x0 Rs1 Rs2 Rd Unused Opcode I-type Opcode Rs1 Rd Immediate J-type Opcode Offset Table 1: instruction formats The MIPS64 uses a fixed length, 32bit instruction format. The three instruction Mike Freeman 09/03/2017
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Introduction to Computer Architectures 2 formats are: immediate (I), register (R) and jump (J), as shown in table 1. Unlike the PicoBlaze assembly language syntax you can explicitly select the registers that will be used as operands ( rs1 and rs2 ) and for the result ( rd ) i.e. source and destination. The supported arithmetic operations are shown in table 2. Instr. Description Format Opcode Operation Syntax DADD Add R 0x20 Rd ← Rs1 + Rs2 DADD rd, rs1, rs2 DADDI Add immediate I 0x08 Rd ← Rs1 + imm DADDI rd, rs1, imm DSUB Subtract R 0x22 Rd ← Rs1 – Rs2 DSUB rd, rs1, rs2 DSUBI Subtract immediate I 0x0a Rd ← Rs1 – imm DSUBI rd, rs1, imm Table 2: arithmetic instructions where rd , rs1 and rs2 are general purpose registers and imm is a 16bit sign extended immediate value. To launch the WinMIPS64 instruction set simulator (ISS) shown in figure2, select: Start -> All Programs -> Hardware Development -> WinMIPS64 This simulator can be downloaded for home use from: Figure 2: WinMIPS64 user interface An example MIPS64 program is shown in figure 3. This program adds together two numbers stored in registers R1 and R2 and copies the result to register R4. Finally to stop the program executing random data that could be in the instruction memory, the halt ’ instruction is executed, flushing the processor’s pipeline and preventing new instructions from being fetched.
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  • Winter '19
  • oussama jadayel
  • Computer Architecture, Central processing unit, Processor register, IMM, Mike Freeman

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