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Introduction to Computer Architectures 1 ICAR Laboratory : CPUSim Lab 1 The aim of this lab is to construct a simulation model of the simple von Neumann CPU and its memory as discussed in the lecture (comparable to EDSAC). A block diagram representation of this computer is shown in figure 1. Using this simulation model, assembly language programs can be executed allowing the user to see the internal processes involved in their execution. The simulation package we will be using is CPUSim: “CPUSim simulates computer architectures at the register-transfer-level (RTL). That is, the basic hardware units from which a hypothetical CPU is constructed e.g. registers, condition bits, memory (RAM) etc. The user does not need to deal with individual transistors or gates on the digital logic level of a machine. The basic units used to define machine instructions consist of microinstructions of a variety of types. The details of how the microinstructions get executed by the hardware are not important at this level.” CPUSim User Manual The CPUSim simulator is written in the Java programming language and runs as a Java application allowing both a Windows or Linux platform to be used. Note , this lab script assumes you are logged into a Windows operating system, however, Linux could equally be used by altering the path names accordingly. The original website which contains this application and additional information on this simulator can be found at: However , for the purposes of this lab we shall be running the simulator locally. To start the CpuSim simulator select : Start -> All programs -> Hardware Development -> CpuSim -> Von_Neumann This will launch the simulator as shown in figure 2. To construct the simulation model the RTL modules are first defined. Describing a CPU’s functionality at this level removes a lot the implementation detail e.g. multiplexers (bug lab), ALU (full adder) etc, simplifying the CPU’s operations to the movement of data between registers (memory elements). The RTL block diagram for this processor is shown in figure 3. Note , the ALU’s functionality (+,–,×,÷) and switching multiplexers (MUX) are implicit in the description and are no longer shown. The CPU has three main registers: Program counter ( PC ) : contains the address in memory of the current instruction being processed i.e. used in fetch phase. Instruction register ( IR ) : used to store the current instruction being performed i.e. processed in the decode phase. Accumulator ( ACC ) : a general purpose register used to store one of the instructions operands and any result produced i.e. used in the decode and execute phases. Mike Freeman 15/11/2016
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Introduction to Computer Architectures 2 Figure 1 : A simple von Neumann CPU and memory Figure 2 : main simulator window Figure 3 : Register transfer level block diagram Mike Freeman 15/11/2016
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Introduction to Computer Architectures 3 In this computer architecture there are also four additional registers: Memory address register ( MAR ) : contains the address of the external memory locations accessed.
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  • Winter '19
  • oussama jadayel
  • Central processing unit, Processor register, Mike Freeman

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