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Introduction to Computer Architectures 1 ICAR Laboratory Answers : PicoBlaze Lab 3 Task 1 Question : can you redesign the logic circuit shown in figureX to generate an enable signal (logic 1) for the input address 0x01 i.e. input port A? To generate a logical 1 output all inputs to the AND must be 1. Therefore, address bits A7 – A1 must be inverted and address line A0 connected directly Reading external memory addresses 0x01 and 0x41 using RDPRT instructions to access switch data. This can be inverted by XOR 0xFF, then output to the LEDs by writing to external memory addresses 0x02 and 0x42 using WRPRT instructions ; # Parallel Port # #EQU pio_A_input, 0x01 #EQU pio_A_output, 0x02 #EQU pio_B_input, 0x41 #EQU pio_B_output, 0x42 ; # Main Program # start: rdprt s0, pio_A_input wrprt s0, pio_A_output rdprt s0, pio_B_input wrprt s0, pio_B_output jump start trap: jump trap Tasks 2 Question : using the XOR instruction can you invert each input port's data i.e. invert each bit: 0 → 1 and 1 → 0, before sending it to the output port? Use the Help tab in the simulator or the online datasheets for more information about this instruction. If you XOR a register will all 0s it is unchanged. If you XOR a register will all 1s it is inverted. rdprt s0, pio_A_input xor s0, 0xFF wrprt s0, pio_A_output Mike Freeman 16/02/2017
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Introduction to Computer Architectures 2 Tasks 3 As script, last chance to check that you program is operating correctly, as once it is downloaded on the FPGA debugging becomes very difficult i.e. no error messages, or
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  • Winter '19
  • oussama jadayel
  • ASCII, Mike Freeman

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