Lab15.pdf

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Introduction to Computer Architectures 1 ICAR Software Laboratory : MIPS64 Lab 2 The aim of this lab is to examine hardware and software techniques that can be used to minimise stall cycles within the MIPS64 processor’s instruction pipeline. To illustrate these techniques we will be looking at the LOAD and STORE instructions. One bottleneck identified early in the development of RISC processors were the delays associated with memory accesses. To minimise this problem only two instruction types can access data memory, as shown in table 1. Instr. Description Format Opcode Operation Syntax LB load byte I 0x23 Rd←MEM[Rs1+imm] LB rd, imm(rs1) LBU load byte unsigned I 0x23 Rd←MEM[Rs1+imm] LBU rd, imm(rs1) LH load half word I 0x23 Rd←MEM[Rs1+imm] LH rd, imm(rs1) LHU load half word unsigned I 0x23 Rd←MEM[Rs1+imm] LHU rd, imm(rs1) LW load word I 0x23 Rd←MEM[Rs1+imm] LW rd, imm(rs1) SB store byte I 0x2b MEM[Rs1+imm] ←Rd SB rd, imm(rs1) SH store half word I 0x2b MEM[Rs1+imm] ←Rd SH rd, imm(rs1) SW store word I 0x2b MEM[Rs1+imm] ←Rd SW rd, imm(rs1) Table 1: arithmetic instructions Where rs1 and rd are general purpose registers and imm is an 16bit sign extended immediate value. In the DLX processor the memory is byte addressable, using a Big Endian byte order. The MIPS64 processor is Bi-endian i.e. it can be configured to store data in memory using Little or Big Endian byte order, as shown in figures 1 & 2. Note , half word (16bit) and word (32bit) accesses must be correctly aligned, as shown in figure 1, e.g. you could not access a half word starting at address Addr+5, valid half words start at Addr+4 and Addr+6. Figure 1 : 32bit Big Endian byte, half word and word ordering Signed and unsigned byte and half word LOADs are defined, allowing correct sign bit replication of higher order register bits e.g. minus one as an 8bit value: 0xFF, within a register this is signed extended to a 64bit value: 0xFFFFFFFFFFFFFFFF, however, if it is an unsigned value it will remain as 0xFF. Mike Freeman 16/03/2017 Byte 0 Byte 1 Byte 2 Byte 3 Addr+0 Addr Half word 0 Addr+4 Word Addr+8 Half word 1 31 24 | 23 16 | 15 8 | 7 0 Bit position Addr+1 Addr+2 Addr+3
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Introduction to Computer Architectures 2 Figure 2 : 32bit Little Endian byte, half word and word ordering Before proceeding ensure that you have disabled data forwarding within the simulator, as described in MIPS64 lab 1.
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  • Winter '19
  • oussama jadayel
  • SEPTA Regional Rail, Endianness, SPARC, Mike Freeman

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