ece571w19_week2_1_lecnotes.pdf - ECE 571 Introduction to SystemVerilog Lecture 3 SystemVerilog built-in data types(wrap-up Structural modeling

ece571w19_week2_1_lecnotes.pdf - ECE 571 Introduction to...

This preview shows page 1 out of 31 pages.

You've reached the end of your free preview.

Want to read all 31 pages?

Unformatted text preview: ECE 571 Introduction to SystemVerilog Lecture 3: SystemVerilog built-in data types (wrap-up) Structural modeling Combinational logic modeling Roy Kravitz Electrical and Computer Engineering Department Maseeh College of Engineering and Computer Science User Defined & Enumerated Types (cont’d) Source material drawn from: • Mark F. and Roy K. ECE 571 lecture slides • SystemVerilog for Design, 2nd Edition by Stuart Sutherland 1 Typedef SystemVerilog permits the user to create new types as in C using typedef Usual scope rules apply…types can be defined: locally (in module) in packages externally (in compilation units) ECE 571 Introduction to SystemVerilog Sharing Types To share a user-defined type put the typedef in a package ECE 571 Introduction to SystemVerilog 2 Enumerated Types SystemVerilog allows you to declare a type with an explicit list of valid values “Classic” Verilog required use of `define or parameter (no error checking on assignments) ECE 571 Introduction to SystemVerilog Enumerated Types (cont’d) Imports definition and type labels ECE 571 Introduction to SystemVerilog 3 Enumerated Types (cont’d) If not using wildcard import you import only the enumerated type but not its labels ECE 571 Introduction to SystemVerilog Enumerated Types (cont’d) SystemVerilog provides shorthand for specifying ranges of labels Creates an enumerated list with the labels RESET, S0..S4, W6..W9 Labels must be unique within their scope (e.g. module, begin…end block, compilation unit, interfaces…) Same label, same scope Same label, different scope ECE 571 Introduction to SystemVerilog 4 Enumerated Type Values SystemVerilog by default represents values for enumerated types as int with first label represented by value of 0, second label with value of 1, etc. User can override (e.g. to map values to specific hardware – one-hot, Gray code, etc) Not required to specify all values Unspecified values continue numbering from previous value SystemVerilog permits an explicit base type (with size) Values must be compatible. ECE 571 Introduction to SystemVerilog Enumerated Type Values (cont’d) Legal or not? Illegal: default base type is int not a 3-bit value Legal: logic is a four-state type Illegal: What is value of LOAD (xx +1)! Illegal: Can only represent two things with one bit ECE 571 Introduction to SystemVerilog 5 Enumerated Types (cont’d) Creating a typedef allows creation of multiple variables of same enumerated type in different places Most “Classic” Verilog and SystemVerilog variable types are loosely typed (any value of any type can be assigned to a variable with automatic conversion to type of variable) Enumerated types are an exception. They are semi-strongly typed and can only be assigned: A label from its enumerated type list Another enumerated type of the same type (declared with same typedef definition) A value cast to the typedef type of the enumerated type ECE 571 Introduction to SystemVerilog Enumerated Types (cont’d) // Legal: both variables of same enumerated type // Legal: foo is of type int, underlying enum is int // Illegal: foo is type int, foo+1 is int not enum type // Illegal: (state + 1) type is int not enum type // Illegal: (state + 1) type is int not enum type // Illegal: (state + 1) type is int not enum type ECE 571 Introduction to SystemVerilog 6 System tasks & methods for enumerated types SystemVerilog provides several special system functions called methods to iterate through the values in an enumerated type list <enum_var>.first <enum_var>.last <enum_var>.next(<N>) <enum_var>.prev(<N>) <enum_var>.num <enum_var>.name // // // // // // // // // // // // Return value of first member in enumerated list of var Return value of last member in enumerated list of var Return value of next member in enumerated list. If N provided return Nth next member Return value of previous member in enumerated list.If N provided return Nth previous member Return the number of labels in the enumerated list of var Return string representation of label for value ECE 571 Introduction to SystemVerilog Type Casting “Classic” Verilog is loosely typed Allows assignment of value of one type to variable or net of different type Value is converted to new type (following rules in Verilog standard) when it is assigned. Typecasting is different - allows value in an expression to be converted (not just during an assignment). Verilog-1995 didn't support type casting. Verilog-2001 added cast for conversion between signed and unsigned types (using $signed and $unsigned). SystemVerilog adds a cast operator (similar to C language but different syntax to preserve compatibility with “Classic” Verilog). Static and Dynamic casts (sometimes called compile-time and run-time) You can cast: type, size, and sign ECE 571 Introduction to SystemVerilog 7 Static Type Casting Cast operator No run-time checking. ECE 571 Introduction to SystemVerilog Dynamic Type Casting Syntax: Examples: Error checking (run-time): Casting a real to an int when value of real is too large to be represented as an int Casting a value to an enumerated type when value doesn't exist in legal set of values Can be called as task (as above, left) which causes runtime error if check fails or system function (as above, right) which returns status value (1 if successful, 0 if fail) ECE 571 Introduction to SystemVerilog 8 Casting Enumerated Types module test(); typedef enum {RED, ORANGE, YELLOW, BLACK, WHITE} color; initial begin color a, b; int i = 7; a = color' (a + 1); color' (a++); b = color' (a++); b = color' (i); $cast(b,a++); $cast(b,(a+1)); // // // // // // // legal because static cast (but no checking!) not legal syntax! Needs to be assigned not legal: can't have ++/-- with enum legal because of cast (but no checking!) not legal: can't have ++/-- with enum legal because dynamic cast (runtime check for legal value) end endmodule ECE 571 Introduction to SystemVerilog Structures (struct) and Unions Source material drawn from: • Mark F. ECE 571 lecture slides • SystemVerilog for Design, 2nd Edition by Stuart Sutherland 9 Struct(ure)s typedef enum {Request, Response, Broadcast} PacketType; typedef struct { int ID; PacketType Type; int CheckSum; byte Data[1024]; } Packet_t; Packet_t SamplePacket; SamplePacket.ID = 0; SamplePacket.Type = Request; . . . ECE 571 Introduction to SystemVerilog Packed Structs Packed structs give you more control over how bits are laid out in memory Consumes 3 words Consumes 3 bytes ECE 571 Introduction to SystemVerilog 10 Packed Structures Represents bit or part selects of vectors ed Structures Packed Structures nts bit or part cked { Valid; Tag; :0] Addr; Entry.Tag; Entry.Addr; Entry.Valid struct structmay may ther otherpacked packed acked arrays packed arrays struct packed { Packed Structs (cont’d) reg [24:0] Entry; bit Valid; `define Valid 24 byte Tag; `define Tag 23:16 bit or part selects of vectors Represents bit [15:0] Addr; `define Addr 15:0 } reg Entry; [24:0] Entry; struct packed { iTag = Entry[`Tag]; iTag = Entry.Tag; Valid; `define Valid 24 iAddr = Entry.Addr; iAddr bit = Entry[`Addr]; byte Tag; `define Tag 23:16 iValid = Entry.Valid iValid bit = Entry[`Valid] [15:0] Addr; `define Addr 15:0 } Entry; 32 0 iTag = Entry[`Tag]; iTag = Entry.Tag; 2 Valid unpacked packed struct may iAddr = Entry[`Addr]; packed struct may iAddr = Entry.Addr; 1 Tag struct contain packed iValid = Entry[`Valid] iValid = Entry.Valid Addr 0 containother other packed structs structsor orpacked packedarrays arrays 24 23 1615 0 32 0 2 unpacked struct Valid 1 Tag Addr 0 37 packed struct packed struct Valid Tag Addr packed packedstruct structmay may contain containother otherpacked packed structs packed structsor or packedarrays arrays packed selects of vecto reg [24:0] Ent `define Valid `define Tag 23 `define Addr 1 iTag = Entry iAddr = Entry iValid = Entry 32 unpacked struct ECE 571 Introduction to SystemVerilog packed struct 37 1 0 24 23 1615 0 SystemVerilog Workshop unpacked DAC2003 Accellera Valid Tag Addr DAC2003 Accellera SystemVerilog Workshop 2 24 23 Valid Ta DAC2003 Accellera SystemVerilog Workshop Initializing Structures ECE 571 Introduction to SystemVerilog 11 Unions Stores several types (mutually exclusive fields) in the same bits ECE 571 Introduction to SystemVerilog Enhanced Literal Values Verilog: Scalable. Change SIZE and this code still works...but not for all cases Doesn’t work for all 1’s (ex: if SIZE > 64 -> Need to edit code) data = ~0 // one’s complement data = -1 // two’s complement data = {SIZE{1'b1}}; // replication SystemVerilog: '0 fill all bits '1 fill all bits 'z fill all bits 'x fill all bits with with with with 0 1 z x …or resort to “tricks” instead No “tricks” needed ECE 571 Introduction to SystemVerilog 12 Constants “Classic” Verilog provides: parameter – Can be redefined during elaboration when instantiated or w/ defparam specparam – Can be redefined at elaboration time from SDF files localparam – Elaboration-time constant that cannot be redefined “Classic” Verilog Parameters: Cannot be assigned to hierarchical reference (part of elaboration) Restricted to modules, static tasks and functions SystemVerilog relaxes/eliminates these constraints with const Can be declared in dynamic contexts (e.g. automatic tasks and functions) Can be assigned a value of net or var instead of a constant expression Can be assigned a value of an object defined elsewhere in design hierarchy const must include a type ECE 571 Introduction to SystemVerilog Structural Modeling Sources: • Mark Faust and Roy Kravitz ECE 571 Lecture Slides • Xiaoyu Song and Roy Kravitz ECE 581 Lecture Slides • SystemVerilog for Design: Overview by Donald Thomas • Logic Design and Verification Using SystemVerilog (Revised) by Donald Thomas 13 Two types of modeling Structural modeling module mux1 (output logic input Focuses on interconnections of things Gate level designs — interconnections of gates Module hierarchy and interconnection regardless of what’s inside each module f, a, b, sel); and #5 g1 (f1, a, nsel), g2 (f2, b, sel); or #5 g3 (f, f1, f2); not g4 (nsel, sel); endmodule: mux1 Procedural modeling Modeling the functionality of logic blocks with statements that look like a programming language look like, and execute like… using always, loops, initial, assign, … module mux2 (output logic input f, a, b, sel); always_comb if (sel) f = b; else f = a; endmodule: mux2 ECE 571 Introduction to SystemVerilog Gate Primitives Some low-level gate primitives are built into SystemVerilog: and, or, nand, nor, xor, xnor, not, buf These are SystemVerilog keywords and cannot be used in any other declaration The meaning of the gates is probably self-evident: xnor is an exclusive NOR gate; buf is a non-inverting buffer. A gate is connected to one or more nets. These nets are listed in parentheses with the output as the first parameter followed by one or more inputs ex: nand g1 (y, a, b); y = ~(a & b) More than one gate instance declared at the same time: nand g1 (y, a, b), g2 (w, c, d); This describes two gates (g1 and g2) You can also specify delay and output strength (not typically done when a circuit is to be synthesized) ECE 571 Introduction to SystemVerilog 14 Gate Primitives (cont’d) ECE 571 Introduction to SystemVerilog Source: Logic Design and Verification Using SystemVerilog, ch12 Modules and Files module and2 ( output wire z, input wire x, y ); assign z = x & y; endmodule The basic unit of a SystemVerilog design is the module This module describes a two-input AND gate The module description starts with the keyword module, followed by the name of the module and a list of outputs and inputs in parentheses followed by a semicolon (;) The module finishes with the keyword endmodule w/ no semicolon The entire module can be contained in single file but it is possible to have more than one module in a file ECE 571 Introduction to SystemVerilog 15 inputa net wire clk, to the wrong port position, the error will Should be connected input wire resetN not be obvious from just looking at the netlist. Another disadvan); tage is that ordered port connections do not clearly document the wire [11:0] design intent. instruct_reg, It is difficult toprogram_data; look at a module instance that is conwire [10:0] program_counter, program_address; nected by port order andstatus_reg, determine tofsr_reg, which port a netoption_reg, is intended wire [ 7:0] tmr0_reg, w_reg, reg_file_out, port_b, port_c, to be connected. Because of port_a, these disadvantages, manytrisa, companies data_bus, alu_a, alu_b; SystemVerilog for company Design discourage thetrisb, use oftrisc, ordered port connections in their wire [ 6:0] reg_file_addr; style wire guidelines. [ 3:0] alu_opcode; 234 wire [ 1:0] alu_a_sel, alu_b_sel; wire reg_file_sel, special_reg_sel, reg_file_enable, Themodule second instance style for to connecting modulesport together in Verilog is to using portone the zero_enable, fourteenth of another module w_reg_enable, carry_enable, skip, names toinstance. specify the name of each port explicitly, along withof the name the isoption, istris, polarity, carry, zero; With ordered port connections, the names each portofdo connect modulenot signal thatItisisconnected to that that port.isThe basicThis syntax for each port matter. the port position critical. requires knowpc_stack pcs ( // module instance with named port connections instances connection is: Port Naming Conventions ing the exact order of the ports for each module instance being con.program_counter(program_counter), .program_address(program_address), nected. .clk(clk), .<port_name>(<net_or_variable_name>) “Classic” Verilog and SystemVerilog provide: .resetN(resetN), .instruct_reg(instruct_reg), ofofa aD-type shown below. exampleinstance instance D-typeflip-flop flip-flopmodule moduleisusing named port AnAnexample Ordered port connections .data_bus(data_bus), .status_reg(status_reg) connections is shown below. Since the flip-flop ports are explicitly );dff d1 (out, /*not used*/, in, clock, reset); named, it is easy to tell to what port a signal is connected, even prom prom ( the actual flip-flop module definition. without seeing The Named connections requirementport to know the exact position of each port of the .dout(program_data), .clk(clk), module being instantiated is.qb(/*not a disadvantage. Unintentional design dff d1 (.q(out), used*/), .address(program_address) errors occur when using the port.rst(reset) order connection .clk(clock), ); syn); can easily.d(in), tax. Modules in complex designs often have dozens of ports. instruction_decode decoder ( instruction_decode decoder ( Using port connection style,port it isposition, not necessary to mainShould athis netnamed be connected to the wrong the error will .alu_opcode(alu_opcode), alu_opcode, alu_a_sel, alu_b_sel, tain the order of the ports for each module instance. By using .alu_a_sel(alu_a_sel), 236 be forw_reg_enable, Design not obvious from just looking at the netlist.SystemVerilog Another disadvanreg_file_sel, .alu_b_sel(alu_b_sel), carry_enable, named portordered connections, the potentialdofornotinadvertent designzero_enable, errors tage is that port connections clearly document the .w_reg_enable(w_reg_enable), polarity, isoption, istris, is reduced, each porttoislook explicitly connected to a specific net. design intent.since It is difficult at a module instance that isinstruct_reg con.reg_file_sel(reg_file_sel), ); .zero_enable(zero_enable), nected by port order and determine to which port a net is intended 9-3 shows a netlist for a disadvantages, small microprocessor, which reptoExample be.carry_enable(carry_enable), connected. Because of these many companies .polarity(polarity), resents a the simplified a MicroChip 8-bit company processor. .option(isoption), discourage use of model orderedofport connectionsPIC in their style.tris(istris), guidelines. .instruct_reg(instruct_reg) ); using port names to connect module instances The second style for connecting modules together in Verilog is to register_files regs ( Named Port connections Ordered Port connections specify the name of each port explicitly, along with the name of the .dout(reg_file_out), signal.tmr0_reg(tmr0_reg), that is connected to that port. The basic syntax for each port .status_reg(status_reg), connection is: ECE 571.fsr_reg(fsr_reg), Introduction to SystemVerilog .port_a(port_a), .port_b(port_b), .<port_name>(<net_or_variable_name>) .port_c(port_c), .trisa(trisa), .trisb(trisb), An example instance of a D-type flip-flop module using named port .trisc(trisc), connections is shown below. Since the flip-flop ports are explicitly .option_reg(option_reg), .w_reg(w_reg), named, it is easy to tell to what port a signal is connected, even .instruct_reg(instruct_reg), without seeing the actual flip-flop module definition. .program_data(program_data), .port_a_pins(port_a_pins), .data_bus(data_bus), dff d1 (.q(out), .qb(/*not used*/), .address(reg_file_addr), .d(in), .clk(clock), .rst(reset) ); .clk(clk), SystemVerilog Enhancements Using this named port connection style, it is not necessary to main- .resetN(resetN), .skip(skip), .reg_file_sel(reg_file_sel), tain .zero_enable(zero_enable), the order of the ports for each module instance. By using .carry_enable(carry_enable), named port connections, the potential for inadvertent design errors .w_reg_enable(w_reg_enable), is reduced, since each port is explicitly connected to a specific net. .reg_file_enable(reg_file_enable), .zero(zero), .carry(carry), Example 9-3 shows a netlist for a small microprocessor, which rep.special_reg_sel(special_reg_sel), .isoption(isoption), resents a simplified model of a MicroChip PIC 8-bit processor. .istris(istris) ); Modules often uses a net name identical to the instantiated module's port name when connecting to the port: SystemVerilog provides three enhancements for making port connections .name ("dot name") .* Interfaces alu alu ( .y(data_bus), .carry_out(carry), .zero_out(zero), .a(alu_a), .b(alu_b), ("dot star") (covered in future lecture) Explicit port <-> net mapping Memory M(.address(address),.data(data),.control(ctrl)); SystemVerilog allows .name: Memory M(.address, .data, .control(ctrl)); The net must match in name, type, and size or an error results ECE 571 Introduction to SystemVerilog 16 SystemVerilog Enhancements (cont’d) .* Causes all ports of the instantiated module to be connected to a net with the same name, type, and size if it exists Memory M(.address(address),.data(data),.control(ctrl)); could be done as: Memory M(.*,.control(ctrl)); The net(s) must match in name, type, and size or an error results 248 SystemVerilog for Design Figure 9-1: Diagram of a simple netlist address ECE 571 Introduction to SystemVerilog ROM program count address next_address data new_address clk address reg next_address next_addr jump_address clock current_addr clk reset_n rstN master_clock master_reset .* (cont’d) Example 9-6: Netlist using SystemVerilog’s .* port connections without aliases module chip (input wire master_clock, input wire master_reset, ...); wire [31:0] address, new_address, next_address; ROM i1 ( .*, // infers .address(address) .data(new_address), .clk(master_clock) ); Different names use .*) program_count i2 ( .*, // infers .next_address(next_address) (can’t .jump_address(new_address), .clock(master_clock), Chapter 9: SystemVerilog Design Hierarchy .reset_n(master_reset) ); address_reg 249 i3 ( .*, // no connections can be inferred .next_addr(next_address), module program_count (output logic [31:0] next_address, .current_addr(address), input wire [31:0] jump_address, .clk(master_clock), input wire clock, reset_n); .rstN(master_reset) ); ... endmodule endmodule module ROM (output wire [31:0] data, input wire [31:0] address, input wire clk); ... endmodule …but ECE 571 Introduction to SystemVerilog module address_reg (output wire [31:0] current_addr, input wire [31:0] next_addr, input wire clk, rstN); ... endmodule using aliases The master_clock in chip sho...
View Full Document

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture