dcug_2.pdf - v1999.10 Design Compiler User Guide 2 Getting a Quick Start 2 This chapter walks you through the basic synthesis design flow(shown in

dcug_2.pdf - v1999.10 Design Compiler User Guide 2 Getting...

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/ 2-1 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide 2Getting a Quick Start2This chapter walks you through the basic synthesis design flow(shown in Figure 2-1). You use the same basic flow for both designexploration and design implementation.The following sections each describe one step of the flow:Developing the HDL FilesStarting the Shell InterfaceSpecifying the LibrariesReading DesignsDefining the Design EnvironmentSelecting Your Compile StrategySetting the Design Constraints
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/ 2-2 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide Optimizing Your Design Analyzing and Debugging Your Design Saving the Design Database Exiting the Shell Interface Design Compiler Session Example
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/ 2-3 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide Figure 2-1 Basic Synthesis Design Flow Define Select Design Environment Compile Strategy Set Design Constraints Optimize the Design Analyze and Debug the Design Read Design Save the Design Database Design Rule Constraints Optimization Constraints Specify Libraries Library Objects Develop HDL Files link_library target_library symbol_library analyze read_file elaborate set_operating_conditions set_wire_load set_drive set_driving_cell set_load set_fanout_load Top-Down Bottom-Up set_max_transition set_max_fanout set_max_capacitance create_clock set_clock_skew set_input_delay set_output_delay set_max_area compile check_design report_area report_constraint report_timing write
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/ 2-4 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide Developing the HDL Files To achieve the best synthesis results, pay close attention to the following issues when developing the HDL files: Managing the design data Partitioning the design Coding the design Managing the Design Data To simplify data exchanges and data searches, develop data organization and revision control methods that all designers adhere to, such as Rules for file creation, maintenance, and deletion A file naming convention A hierarchical directory structure for design data For more information, see Chapter 3, “Working With Design Files.” Partitioning the Design Partitioning a design effectively can enhance synthesis results. Efficient partitioning can also help obtain optimal results by reducing compile time and simplifying constraint definition. Keep the following in mind when you partition your design: To achieve the best synthesis results,
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/ 2-5 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide - Keep related combinational logic in the same VHDL entity or Verilog module. - Merge resources in the same VHDL process or Verilog always block. - Keep user-defined resources with the logic they drive. - Separate blocks having different goals.
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