dcug_1.pdf - v1999.10 Design Compiler User Guide 1...

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/ 1-1 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide 1 Introduction to Design Compiler 1 Design Compiler is the core of the Synopsys synthesis software products. It provides constraint-driven optimization and supports a wide range of design styles. The Design Compiler tools synthesize your HDL description into a technology-dependent, gate-level design. Design Compiler optimizes combinational or sequential designs for speed, area, and power, and supports both flat and hierarchical designs. Figure 1-1 Design Compiler Overview VHDL Source Verilog Source Other Input Formats VHDL Compiler HDL Compiler compile Design Compiler Mapped, Technology- Dependent Netlist
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/ 1-2 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide DesignCompilerprovideslinkstoelectronicdesignautomation(EDA) tools, such as place and route tools, and post layout resynthesis techniques, such as in-place optimization. These EDA tool links enable sharing of information (such as forward-directed constraints and delays) between Design Compiler and external tools. This chapter includes the following sections: Design Compiler Products User Interfaces Supported File Formats Supported File Formats License Requirements Resource Requirements High-Level Design Flow Design Compiler Products Synopsys provides a spectrum of Design Compiler products, which varyinthecomplexityofthefeaturesoffered.Choosetherightproduct for your design environment, based on your synthesis requirements. Using the Design Compiler products, you can Produce fast, area-efficient ASIC designs by using user-specified gate-array, FPGA, or standard-cell libraries Translate designs from one technology to another
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/ 1-3 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide Explore design tradeoffs involving design constraints such as timing, area, and power under various loading, temperature, and voltage conditions Synthesize and optimize a finite state machine, including automatic state assignment and state minimization Integrate netlist input and netlist or schematic output into third- party environments while still supporting delay information and place and route constraints Create and partition hierarchical schematics automatically The Design Compiler products include DC Professional DC Expert DC Expert Plus DC Ultra DC Ultra Plus Figure 1-2 shows the relationship between the features in the Design Compiler products.
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/ 1-4 HOME CONTENTS INDEX v1999.10 Design Compiler User Guide Figure 1-2 Design Compiler Products The following sections describe these products. DC Professional The DC Professional tools are applied to typical ASIC designs that employ CMOS technology. These designs can utilize multiple clocks; however, the clocks must have the same frequency. DC Professional does not support time borrowing for latch-based designs.
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