NewForthVM.doc - Updating the Forth Virtual Machine EuroForth 2008 Updating the Forth Virtual Machine Stephen Pelc MicroProcessor Engineering 133 Hill

NewForthVM.doc - Updating the Forth Virtual Machine...

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Updating the Forth Virtual Machine EuroForth 2008 Updating the Forth Virtual Machine Stephen Pelc MicroProcessor Engineering 133 Hill Lane Southampton SO15 5AF England tel: +44 (0)23 8631 441 fax: +44 (0)23 8033 9691 net: [email protected] web: Abstract The canonical Forth Virtual machine has remained essentially the same since its inception. Modern silicon implementations and compiler techniques indicate that the VM as used in practice differs from this model. It is time to consider overhauling the canonical Forth Virtual Machine. In particular, the addition of address registers is considered. Introduction Classical or canonical Forth views the world as a CPU connected to main memory and two stacks which are not addressable, and are quite separate from main memory. C views the world as a CPU connected to memory, which includes a list of frames (usually a stack of frames) which must be in addressable memory. By adding the necessary registers for the frame stack to the canonical Forth machine, we arrive at the basic design of the SENDIT VM, which was discussed in various papers in the late 1990s. SENDIT (EP9152) was a project carried out under the European Union’s ESPRIT research and development programme. SENDIT was based upon the results of a preceding project, PROCIC EP5497, and produced tools for the development of heterogeneous networks for use in embedded and real time applications. C P U M a i n M e m o r y D a t a S t a c k R e t u r n S t a c k C P U M a i n M e m o r y i n c l u d i n g F r a m e S t a c k F o r t h V M C V M
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Updating the Forth Virtual Machine EuroForth 2008 The SENDIT VM looks remarkably similar to other stack machine CPUs derived from a Forth architecture and designed to execute C efficiently. Another branch of the Forth virtual machine has been called machineForth, and appears in software implementations such as ColorForth and various CPUs from iTV, Ultratechnology and IntellaSys, most lately in the SEAForth S24 multicore chips. Other CPU core designs include MicroCore and designs from Bernd Paysan, Brad Eckert and Chris Bailey. What distinguishes these cores is that they introduce data cells, registers and operations that are unsupported by the canonical Forth machine. In the description I have chosen not to include the TOS, NOS and TOR virtual registers. TOS and NOS are common across virtually all implementations as ALU inputs and outputs. TOR has wide variation in implementation for anything other than to hold a return address.
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