lecture_5 - Lecture 5 CMOS Transistor Theory Mark McDermott Electrical and Computer Engineering The University of Texas at Austin VLSI-1 Class Notes

lecture_5 - Lecture 5 CMOS Transistor Theory Mark...

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VLSI-1 Class Notes Lecture 5: CMOS Transistor Theory Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/13/18
VLSI-1 Class Notes Outline § Introduction § MOS Capacitor § nMOS I-V Characteristics § pMOS I-V Characteristics § Gate and Diffusion Capacitance § MOS Channel resistance § Resistors & RC approximation 9/13/18 Page 2
VLSI-1 Class Notes Introduction § So far, we have treated transistors as ideal switches § An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships § Transistor gate, source, drain all have capacitance I = C ( D V/ D t) -> D t = (C/I) D V Capacitance and current determine speed 9/13/18 Page 3
VLSI-1 Class Notes Electrical Properties of MOS Devices § Necessary to understand the basic electrical properties of the MOS transistor (geometry => electrical), e.g., delay/power Ensure that the circuits are robust Create working layouts Predict delays and power consumption § As technology advances and circuit dimensions scale down, electrical effects become more important Secondary/non-ideal effects (next lecture) 9/13/18 Page 4
VLSI-1 Class Notes MOS Capacitor § Gate and body form MOS capacitor § Operating modes Accumulation Depletion Inversion polysilicon gate (a) silicon dioxide insulator p-type body + - V g < 0 (b) + - 0 < V g < V t depletion region (c) + - V g > V t depletion region inversion region 9/13/18 Page 5
VLSI-1 Class Notes The nMOS Transistor § Gate is insulated from substrate by thin oxide Resistance of oxide is > 10 12 W , so current ~ 0 § Two types of nMOS transistor Enhancement mode: non conducting when gate voltage V gs = V sb (source voltage) ( normally used ) Depletion mode: conducting when V gs = V sb Moderately doped p- type substrate (or well) in which two heavily doped n+ regions, the Source and Drain are diffused 9/13/18 Page 6
VLSI-1 Class Notes Terminal Voltages § Mode of operation depends on V g , V d , V s V gs = V g – V s V gd = V g – V d V ds = V d – V s = V gs - V gd § Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds ³ 0 § nMOS body is grounded; for simple designs, assume source is grounded too § Three regions of operation Cutoff Linear Saturation V g V s V d V gd V gs V ds + - + - + - 9/13/18 Page 7
VLSI-1 Class Notes nMOS Cutoff § No channel I ds 0 + - V gs = 0 n+ n+ + - V gd p-type body b g s d 9/13/18 Page 8
VLSI-1 Class Notes nMOS Linear § Channel forms § Current flows from d to s e - from s to d § I ds increases with V ds Similar to linear resistor § Since there is a threshold voltage ( V t ) required to invert the charge under the gate, this means that the effective gate voltage is: + - V gs > V t n+ n+ + - V gd = V gs + - V gs > V t n+ n+ + - V gs > V gd > V t V ds = 0 0 < V ds < V gs -V t p-type body p-type body b g s d b g s d I ds 9/13/18 Page 9 t gs g V V V - =
VLSI-1 Class Notes nMOS Saturation § Channel pinches off § I ds independent of V ds § Current saturates § Similar to current source + - V gs > V t n+ n+ + - V gd < V t V ds > V gs -V t p-type body b g s d I ds 9/13/18 Page 10

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