lecture_7.pdf - Lecture 7 CMOS DC Transient Response Mark McDermott Electrical and Computer Engineering The University of Texas at Austin VLSI-1 Class

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VLSI-1 Class Notes Lecture 7: CMOS DC & Transient Response Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/20/18
VLSI-1 Class Notes Agenda § DC Response § Logic Levels and Noise Margins § Transient Response § Delay Estimation 9/20/18 Page 2
VLSI-1 Class Notes DC Response § DC Response: V out vs. V in for a gate § Ex: Inverter When V in = 0 -> V out = V DD When V in = V DD -> V out = 0 In between, V out depends on transistor size and current By KCL, we know that I dsn = |I dsp | We could solve equations But graphical solution gives more insight I dsn I dsp V out V DD V in 9/20/18 Page 3
VLSI-1 Class Notes Transistor Operation Review § Current depends on region of transistor behavior § For what Vin and Vout are nMOS and pMOS in Cutoff? Linear? Saturation? 0 V GS = +5V V GS = +4V V GS = +3V V GS = +2V V GS = +1V 0 1 2 3 4 5 6 Drain-Source Voltage, V DS (volts) Drain Current, I DS ( μ a) Saturation Region Linear Region 10 20 30 40 50 60 9/20/18 Page 4
VLSI-1 Class Notes nMOS Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn I dsn I dsp V out V DD V in V gsn = V in V dsn = V out 9/20/18 Page 5
VLSI-1 Class Notes pMOS Operation Cutoff Linear Saturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp – V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp – V tp V out < V in - V tp I dsn I dsp V out V DD V in V gsp = V in - V DD V dsp = V out - V DD V tp < 0 9/20/18 Page 6
VLSI-1 Class Notes I-V Characteristics § Make pMOS wider than nMOS such that βn = βp V gsn5 V gsn4 V gsn3 V gsn2 V gsn1 V gsp5 V gsp4 V gsp3 V gsp2 V gsp1 V DD -V DD V dsn -V dsp -I dsp I dsn 0 9/20/18 Page 7
VLSI-1 Class Notes Current vs. Vout, Vin V in5 V in4 V in3 V in2 V in1 V in0 V in1 V in2 V in3 V in4 I dsn , |I dsp | V out V DD 9/20/18 Page 8
VLSI-1 Class Notes Load Line Analysis § For a given V in : Plot I dsn , I dsp vs. V out V out must be where |currents| are equal V in5 V in4 V in3 V in2 V in1 V in0 V in1 V in2 V in3 V in4 I dsn , |I dsp | V out V DD I dsn I dsp V out V DD V in 9/20/18 Page 9
VLSI-1 Class Notes Load Line Analysis § V in = 0 V in0 V in0 I dsn , |I dsp | V out V DD 9/20/18 Page 10
VLSI-1 Class Notes Load Line Analysis § V in = 0.2V DD V in1 V in1 I dsn , |I dsp | V out V DD 9/20/18 Page 11
VLSI-1 Class Notes Load Line Analysis § V in = 0.4V DD V in2 V in2 I dsn , |I dsp | V out V DD 9/20/18 Page 12
VLSI-1 Class Notes Load Line Analysis § V in = 0.6V DD V in3 V in3 I dsn , |I dsp | V out V DD 9/20/18 Page 13
VLSI-1 Class Notes Load Line Analysis § V in = 0.8V DD V in4 V in4 I dsn , |I dsp | V out V DD 9/20/18 Page 14
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