Lab 3.pdf - Lab 3 \u2013Implementing Half and Full Subtractor from Logic Gate I Introduction 1 Activity \u2022 \u2022 \u2022 \u2022 Implementing and simulating the

Lab 3.pdf - Lab 3 –Implementing Half and Full Subtractor...

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Lab 3 Implementing Half and Full Subtractor from Logic Gate I. Introduction 1. Activity Implementing and simulating the operation of half-subtractor Implementing and simulating the operation of full-subtractor Implementing and simulating of 4-bits parallel subtractor Impl ementing and simulating of 2’s complement adder/subtractor 2. Theory Half subtractor and Full subtractor are one of the most important combinational circuit used, they are basically electronic devices or we can say logical circuits which performs subtraction of two binary digits. II. Lab Experiment 1. Half Subtractor Half subtractor is a combinational circuit which is capable of performing subtraction of 2-bit binary digits. Practice a. Implementing this half-subtractor from both formula by using logic gate The half subtractor Boolean expressions are: D = (X’Y + XY’) = X Y B = X’Y We get the logic gate as following:
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b. Using truth table to verify the operation. Half subtractor truth table: INPUT OUTPUT X Y D B 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 c. Implementing and simulating half-subtractor through simulation software (Quartus Prime).
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  • Fall '17
  • tola
  • Logic gate

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