ch7

ch7 - Solutions Chapter 7 7.1 In any circuit the transistor...

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Solutions Chapter 7 7.1. In any circuit, the transistor operation can be understood by examining the superposition of the transistor characteristics and the conditions imposed by the circuit (the load line). What differentiates, then, a digital transistor circuit from an analog one? The difference is in how the circuit is operated. In a digital circuit, the gate voltage is varied between two values, one that produces cutoff and one in the sublinear region. In an analog circuit, the gate voltage is normally varied within the current saturation range, producing proportional changes in the output (drain) voltage. 7.2. In modern FETs, the gate is usually degenerately doped silicon, whose Fermi level is essentially at the bottom of the conduction band edge (for an NFET) or at the top of the valence band edge (for a PFET). a) Draw an energy band diagram similar to Figure 7.5b, except making the transistor a PFET. b) Suppose the device is an NFET, but the gate is made of metal (as was done in the early days). Draw the energy band diagram. Take Φ M < Φ S . The energy band diagram is: Anderson & Anderson 1 11/19/2007 Solutions Chapter 7

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7.3. For the transistor of Figure P7.1, by how much should the gate voltage be changed to produce inversion? Threshold? Assume half the applied voltage appears across the oxide and half across the semiconductor. If the device in the figure is at equilibrium, is this an enhancement or a depletion FET? We need to bend the bands in the Si by an additional 0.1 eV to just invert the surface, meaning the gate voltage should be increased by 2 × 0.1=0.2V. To produce threshold, the surface should be inverted by 0.3 eV, requiring another 0.3eV of band bending or 0.6V. Thus the change in gate voltage required to reach threshold if 0.6+0.2=0.8V. As no channel exists at equilibrium, this is an enhancement device. 7.4. For each of the transistors of Figure 7.10, a) What is the polarity of the threshold voltage V T ? b) What is the polarity of V DS that should be used? c) When V GS =0 (equilibrium), is the transistor on or off? d) Is the current I D carried by electrons or holes? e) For V GS > V T , is the current I D carried primarily by drift or diffusion? Enhancement NFET Enhancement PFET Depletion NFET Depletion PFET V T Positive Negative Negative Positive V DS Positive Negative Positive Negative V GS =0 Off Off On On Carriers Electrons Holes Electrons Holes Current Drift Drift Drift Drift Anderson & Anderson 2 11/19/2007 Solutions Chapter 7
7.5 An NFET is fabricated with a degenerately doped n-type gate. What doping concentration in the p-type substrate is needed for there to be a channel even with no voltage applied? Assume half the built-in voltage is dropped across the oxide and half across the silicon. Let the definition of “a channel exists” be that the surface of the silicon is inverted such that the electron concentration at the Si/SiO 2 interface is equal to the hole concentration in the bulk p-type silicon.. Is the doping you found a minimum or a maximum required to create a depletion-type device?

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