ch8

# ch8 - SOLUTIONS TO PROBLEMS FROM CHAPTER 8 8.1 Figure P8.1...

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SOLUTIONS TO PROBLEMS FROM CHAPTER 8 8.1. Figure P8.1. shows the I D - V GS characteristic for an NMOS with V DS =50 mV. It is known for this device that W= 10 μ m, L =0.5 μ m, and t ox =5 nm. a) Find the threshold voltage Since V DS =50 mV and L =0.5 μ m, the average field in the channel is 0.1 V/ μ m=1kV/cm and the device is not in the velocity saturation region. Thus the expression (Equation (8.4)) ( 29 ( 29 ' 0 1 2 ox DS DS D GS T GS T WC V V I V V L V V μ θ = - - + - can be used. The threshold is extrapolated from the linear region, and using Equation (8.8), 0.05 0.5 2 2 DS T T V V V V + = = + Therefore V T =0.475V. b) Find μ 0 , the electron channel mobility at threshold. The slope of the linear region is about 160 μ A/(0.5V)=0.32mA/V. From Equation (8.7), we have ' 0 D ox DS GS dI WC V dV L μ = Anderson & Anderson 1 November 19, 2007 Solutions Chapter 8

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C ox ' = ε ox t ox = 3.9 ( 29 8.85 × 10 - 14 F / cm ( 29 5 × 10 - 7 cm = 6.9 × 10 - 7 F / cm 2 Solving for μ 0 we have ( 29 3 2 0 ' 7 2 0.5 0.32 10 / 460 10 6.9 10 / 0.05 D GS ox DS dI L dV A V cm WC V F cm V V s μ - - × = = = × 8.2. A particular MOSFET process produces C B ' =10 -7 F/cm 2 and I 0 = 4 × 1 0 - 2 0 A , and a threshold voltage of V T =0.5V. For gate oxide thicknesses of 6.5 nm and 4 nm, find n and S . Which device is better, and why? For t ox =6.5 nm, C o x ' = ε o x t o x = 3 . 9 8 . 8 5 × 1 0 - 1 4 F / c m ( 29 6 . 5 × 1 0 - 7 c m = 5 . 3 × 1 0 - 7 F / c m n = 1 + C B ' C o x ' = 1 + 1 0 - 7 5 . 3 × 1 0 - 7 = 1 . 1 9 S = 2 . 3 k T n q = 7 1 m V / d e c a d e For the 4 nm oxide, ' 7 8.63 10 / ox C F cm - = × =, and n = 1 + C B ' C ox ' = 1 + 10 - 7 8.63 × 10 - 7 = 1.12 S = 2 . 3 k T n q = 2 . 3 ( 29 0 . 0 2 6 ( 29 1 . 1 2 ( 29 = 6 7 m V / d e c a d e The 4 nm device is better. The swing S is smaller, resulting in a sharper turn-on and thus permitting a reduced threshold voltage and a reduced power supply voltage and reduced power consumption. 8.3. a) Find W p / W n needed to match I Dsat for CMOS transistors if μ l f n = 5 0 0 c m 2 / V s , μ lfp =200 cm 2 /V·s, L= 0.5 μ m, and V GS - V T =2.6 V. Assume that 6 4 10 / sat v cm s = × s. From Figure 8.6, we want W p W n = 1 . 3 . b) Find V DSsat for the NMOS and the PMOS. Anderson & Anderson 2 November 19, 2007 Solutions Chapter 8
( 29 ( 29 ( 29 ( 29 1 2 ( ) 1 2 2 6 4 2 6 4 2 v 1 1 v 2 500 2.6 4 10 0.5 10 1 1 4 10 0.5 10 500 1.09 lfn GS T sat DSsat n nFET lfn sat nFET V V V L L cm cm V V s s cm cm cm cm s V s V μ μ - - - = + - × = × + - × × = (or one could read it off Figure 7.31) Similarly, ( 29 ( 29 ( 29 ( 29 1 2 ( ) 1 2 2 6 4 2 6 4 2 1 1 2 200 2.6 4 10 0.5 10 1 1 4 10 0.5 10 200 1.49 lfp GS T sat DSsat p pFET lfp sat pFET V V v V L v L cm cm V V s s cm cm cm cm s V s V μ μ - - - = + - × = × + - × × = c) Adjust the length of the NFET to equalize the V DSsat ’s . What should the new W p W n be to keep the I Dsat ’s equal?

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